Patents by Inventor SHENG-PIN YANG

SHENG-PIN YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11855028
    Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING
    Inventors: Ting-Li Yang, Po-Hao Tsai, Yi-Wen Wu, Sheng-Pin Yang, Hao-Chun Liu
  • Publication number: 20230369269
    Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Ting-Li Yang, Po-Hao Tsai, Yi-Wen Wu, Sheng-Pin Yang, Hao-Chun Liu
  • Publication number: 20230154788
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first conductive line over a substrate. The semiconductor device structure includes a first protection cap over the end portion. The first protection cap and the first conductive line are made of different conductive materials, and the first protection cap exposes a peripheral region of a top surface of the end portion. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The semiconductor device structure includes a conductive via structure passing through the first photosensitive dielectric layer and connected to the first protection cap.
    Type: Application
    Filed: January 13, 2023
    Publication date: May 18, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Li YANG, Wei-Li HUANG, Sheng-Pin YANG, Chi-Cheng CHEN, Hon-Lin HUANG, Chin-Yu KU, Chen-Shien CHEN
  • Patent number: 11557508
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first conductive line over a substrate. The semiconductor device structure includes a first protection cap over the first conductive line. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The semiconductor device structure includes a conductive via structure passing through the first photosensitive dielectric layer and connected to the first protection cap. The semiconductor device structure includes a second conductive line over the conductive via structure and the first photosensitive dielectric layer. The semiconductor device structure includes a second protection cap over the second conductive line. The semiconductor device structure includes a second photosensitive dielectric layer over the first photosensitive dielectric layer, the second conductive line, and the second protection cap.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: January 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Li Yang, Wei-Li Huang, Sheng-Pin Yang, Chi-Cheng Chen, Hon-Lin Huang, Chin-Yu Ku, Chen-Shien Chen
  • Publication number: 20220230978
    Abstract: A semiconductor device includes a substrate; an interconnect structure over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to conductive features of the interconnect structure; a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, where the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, where the dummy bump is separated from the conductive line by the conformal second passivation layer.
    Type: Application
    Filed: May 21, 2021
    Publication date: July 21, 2022
    Inventors: Ting-Li Yang, Po-Hao Tsai, Yi-Wen Wu, Sheng-Pin Yang, Hao-Chun Liu
  • Patent number: 11069652
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu, Chin-Yu Ku, De-Dui Liao, Kuo-Chio Liu, Kai-Di Wu, Kuo-Pin Chang, Sheng-Pin Yang, Isaac Huang
  • Publication number: 20200381293
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first conductive line over a substrate. The semiconductor device structure includes a first protection cap over the first conductive line. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The semiconductor device structure includes a conductive via structure passing through the first photosensitive dielectric layer and connected to the first protection cap. The semiconductor device structure includes a second conductive line over the conductive via structure and the first photosensitive dielectric layer. The semiconductor device structure includes a second protection cap over the second conductive line. The semiconductor device structure includes a second photosensitive dielectric layer over the first photosensitive dielectric layer, the second conductive line, and the second protection cap.
    Type: Application
    Filed: August 14, 2020
    Publication date: December 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Li YANG, Wei-Li HUANG, Sheng-Pin YANG, Chi-Cheng CHEN, Hon-Lin HUANG, Chin-Yu KU, Chen-Shien CHEN
  • Patent number: 10748810
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first conductive line over a substrate. The method includes forming a first protection cap over a first portion of the first conductive line. The first protection cap and the first conductive line are made of different conductive materials. The method includes forming a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The method includes forming a first opening in the first photosensitive dielectric layer and over the first protection cap. The method includes forming a conductive via structure and a second conductive line over the first conductive line. The conductive via structure is in the first opening and over the first protection cap, and the second conductive line is over the conductive via structure and the first photosensitive dielectric layer.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Li Yang, Wei-li Huang, Sheng-Pin Yang, Chi-Cheng Chen, Hon-Lin Huang, Chin-Yu Ku, Chen-Shien Chen
  • Publication number: 20200152599
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.
    Type: Application
    Filed: January 14, 2020
    Publication date: May 14, 2020
    Inventors: ALEXANDER KALNITSKY, YI-YANG LEI, HSI-CHING WANG, CHENG-YU KUO, TSUNG LUNG HUANG, CHING-HUA HSIEH, CHUNG-SHI LIU, CHEN-HUA YU, CHIN-YU KU, DE-DUI LIAO, KUO-CHIO LIU, KAI-DI WU, KUO-PIN CHANG, SHENG-PIN YANG, ISAAC HUANG
  • Patent number: 10566204
    Abstract: In some embodiments, a method of forming an integrated circuit includes providing a semiconductor substrate having an electronic circuit formed on a front side, and having a first material layer located over a second side of the substrate and a second material layer located between the first material layer and the second side. At least a portion of the first material layer is removed using a first chemical etching process, thereby exposing the second material layer. At least a portion of the second material layer is removed using a second chemical etching process. A portion of the substrate is then mechanically removed from the second side.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: February 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jian Jun Kong, She Yu Tang, Tian Yi Zhang, Qin Xu Yu, Sheng Pin Yang
  • Patent number: 10535629
    Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including an IMD layer disposed over the first substrate and a plurality of conductive bumps disposed in the IMD layer; receiving a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the IMD layer is exposed through the patterned adhesive; and bonding the first substrate with the second substrate, wherein a top surface of the at least portion of the IMD layer is exposed through the patterned adhesive after bonding the first substrate with the second substrate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu, Chin-Yu Ku, De-Dui Liao, Kuo-Chio Liu, Kai-Di Wu, Kuo-Pin Chang, Sheng-Pin Yang, Isaac Huang
  • Publication number: 20190371653
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first conductive line over a substrate. The method includes forming a first protection cap over a first portion of the first conductive line. The first protection cap and the first conductive line are made of different conductive materials. The method includes forming a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The method includes forming a first opening in the first photosensitive dielectric layer and over the first protection cap. The method includes forming a conductive via structure and a second conductive line over the first conductive line. The conductive via structure is in the first opening and over the first protection cap, and the second conductive line is over the conductive via structure and the first photosensitive dielectric layer.
    Type: Application
    Filed: May 29, 2018
    Publication date: December 5, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Li YANG, Wei-Li HUANG, Sheng-Pin YANG, Chi-Cheng CHEN, Hon-Lin HUANG, Chin-Yu KU, Chen-Shien CHEN
  • Publication number: 20190214263
    Abstract: In some embodiments, a method of forming an integrated circuit includes providing a semiconductor substrate having an electronic circuit formed on a front side, and having a first material layer located over a second side of the substrate and a second material layer located between the first material layer and the second side. At least a portion of the first material layer is removed using a first chemical etching process, thereby exposing the second material layer. At least a portion of the second material layer is removed using a second chemical etching process. A portion of the substrate is then mechanically removed from the second side.
    Type: Application
    Filed: February 22, 2019
    Publication date: July 11, 2019
    Inventors: Jian Jun KONG, She Yu TANG, Yian Yi ZHANG, Qin Xu YU, Sheng Pin YANG
  • Patent number: 10269703
    Abstract: A semiconductor device includes: a first conductive line disposed on a substrate, a second conductive line disposed on the substrate, and the second conductive line separated with the first conductive line by a trench; an insulating layer disposed on the first conductive line and the second conductive line, and filled the trench between the first conductive line and the second conductive line; and a magnetic film having a first surface and a second surface opposite to the first surface, and the first surface disposed on the insulating layer; wherein the first surface has a first concave directly above the trench, and the first concave has a first obtuse angle of at least 170 degree.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Yu Ku, Sheng-Pin Yang, Chen-Shien Chen, Hon-Lin Huang, Chien-Chih Chou, Ting-Li Yang
  • Publication number: 20190115313
    Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including an IMD layer disposed over the first substrate and a plurality of conductive bumps disposed in the IMD layer; receiving a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the IMD layer is exposed through the patterned adhesive; and bonding the first substrate with the second substrate, wherein a top surface of the at least portion of the IMD layer is exposed through the patterned adhesive after bonding the first substrate with the second substrate.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 18, 2019
    Inventors: ALEXANDER KALNITSKY, YI-YANG LEI, HSI-CHING WANG, CHENG-YU KUO, TSUNG LUNG HUANG, CHING-HUA HSIEH, CHUNG-SHI LIU, CHEN-HUA YU, CHIN-YU KU, DE-DUI LIAO, KUO-CHIO LIU, KAI-DI WU, KUO-PIN CHANG, SHENG-PIN YANG, ISAAC HUANG
  • Patent number: 10249504
    Abstract: In some embodiments, a method includes wet-etching a first film layer of a plurality of film layers stacked on a semiconductor substrate, the wet-etching of the first film layer performed using a first chemical, where the first film layer is an outermost film layer stacked on the semiconductor substrate. The method further includes wet-etching a second film layer of the plurality of film layers using a second chemical. The method also includes using a mechanical grinding wheel to grind the semiconductor substrate to reduce a thickness of the semiconductor substrate.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: April 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jian Jun Kong, She Yu Tang, Tian Yi Zhang, Qin Xu Yu, Sheng Pin Yang
  • Publication number: 20190067017
    Abstract: In some embodiments, a method includes wet-etching a first film layer of a plurality of film layers stacked on a semiconductor substrate, the wet-etching of the first film layer performed using a first chemical, where the first film layer is an outermost film layer stacked on the semiconductor substrate. The method further includes wet-etching a second film layer of the plurality of film layers using a second chemical. The method also includes using a mechanical grinding wheel to grind the semiconductor substrate to reduce a thickness of the semiconductor substrate.
    Type: Application
    Filed: January 8, 2018
    Publication date: February 28, 2019
    Inventors: Jian Jun Kong, She Yu Tang, Tian Yi Zhang, Qin Xu Yu, Sheng Pin Yang
  • Patent number: 10163849
    Abstract: A method of manufacturing a semiconductor structure, including receiving a first substrate including a plurality of conductive bumps disposed over the first substrate; receiving a second substrate; disposing an adhesive over the first substrate; removing a portion of the adhesive to expose at least one of the plurality of conductive bumps; and bonding the first substrate with the second substrate.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu, Chin-Yu Ku, De-Dui Liao, Kuo-Chio Liu, Kai-Di Wu, Kuo-Pin Chang, Sheng-Pin Yang, Isaac Huang
  • Publication number: 20180151493
    Abstract: A semiconductor device includes: a first conductive line disposed on a substrate, a second conductive line disposed on the substrate, and the second conductive line separated with the first conductive line by a trench; an insulating layer disposed on the first conductive line and the second conductive line, and filled the trench between the first conductive line and the second conductive line; and a magnetic film having a first surface and a second surface opposite to the first surface, and the first surface disposed on the insulating layer; wherein the first surface has a first concave directly above the trench, and the first concave has a first obtuse angle of at least 170 degree.
    Type: Application
    Filed: February 16, 2017
    Publication date: May 31, 2018
    Inventors: CHIN-YU KU, SHENG-PIN YANG, CHEN-SHIEN CHEN, HON-LIN HUANG, CHIEN-CHIH CHOU, TING-LI YANG
  • Publication number: 20180047701
    Abstract: A method of manufacturing a semiconductor structure, including receiving a first substrate including a plurality of conductive bumps disposed over the first substrate; receiving a second substrate; disposing an adhesive over the first substrate; removing a portion of the adhesive to expose at least one of the plurality of conductive bumps; and bonding the first substrate with the second substrate.
    Type: Application
    Filed: October 23, 2017
    Publication date: February 15, 2018
    Inventors: ALEXANDER KALNITSKY, YI-YANG LEI, HSI-CHING WANG, CHENG-YU KUO, TSUNG LUNG HUANG, CHING-HUA HSIEH, CHUNG-SHI LIU, CHEN-HUA YU, CHIN-YU KU, DE-DUI LIAO, KUO-CHIO LIU, KAI-DI WU, KUO-PIN CHANG, SHENG-PIN YANG, ISAAC HUANG