Patents by Inventor Sheng-Wei Yang
Sheng-Wei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12272679Abstract: A display panel and a manufacturing method thereof are provided. The display panel includes a circuit substrate and a plurality of micro light-emitting diode structures. The micro light-emitting diode structures each include a micro light-emitting chip and a molding structure. The micro light-emitting chip is electrically bonded to the circuit substrate, and includes a first surface, a second surface, and a peripheral surface. The first surface is located on a side of the micro light-emitting chip facing the circuit substrate. The second surface is disposed opposite to the first surface. The peripheral surface connects the first surface and the second surface. The molding structure surrounds the peripheral surface and encloses the second surface of the micro light-emitting chip. The molding structure extends in a direction away from the circuit substrate and forms an inner side wall. The inner side wall and the second surface constitute an accommodating portion.Type: GrantFiled: January 6, 2022Date of Patent: April 8, 2025Assignee: PlayNitride Display Co., Ltd.Inventors: Shiang-Ning Yang, Sheng-Yuan Sun, Loganathan Murugan, Yu-Yun Lo, Bo-Wei Wu
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Patent number: 12272715Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. A plurality of photodetectors is disposed in the semiconductor substrate. An isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.Type: GrantFiled: June 21, 2021Date of Patent: April 8, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chan Li, Hau-Yi Hsiao, Che Wei Yang, Sheng-Chau Chen, Cheng-Yuan Tsai
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Patent number: 12249493Abstract: A method includes loading a wafer over a wafer chuck in a process chamber; performing a deposition process on the loaded wafer; supplying a fluid medium to a fluid guiding structure in the wafer chuck from a fluid inlet port on the wafer chuck, the fluid guiding structure comprising a plurality of arc-shaped channels fluidly communicated with each other; guiding the fluid medium from a first one of the arc-shaped channels of the fluid guiding structure to a second one of the arc-shaped channels of the fluid guiding structure. The second one of the arc-shaped channels of the fluid guiding structure is concentric with the first one of the arc-shaped channels of the fluid guiding structure from a top view.Type: GrantFiled: February 22, 2023Date of Patent: March 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sheng-Chun Yang, Yi-Ming Lin, Po-Wei Liang, Chu-Han Hsieh, Chih-Lung Cheng, Po-Chih Huang
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Publication number: 20250077357Abstract: A method for backing up a configuration file of a computer device is implemented by a baseboard management controller, and includes steps of: mounting a first partition, a second partition and a third partition of a flash memory storage device of the computer device; storing a copy of the configuration file in at least one of the first partition, the second partition and the third partition that has been mounted successfully as a backup; running an operating system stored in the flash memory storage device; and neither reading nor writing to the third partition while running the OS.Type: ApplicationFiled: April 24, 2024Publication date: March 6, 2025Applicant: Mitac Computing Technology CorporationInventors: Hung-Ta LIN, Sheng-Min CHEN, Po-Wei YANG, Ying-Jie LIU
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Publication number: 20250069975Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.Type: ApplicationFiled: November 12, 2024Publication date: February 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-An Kuo, Ching-Jung Yang, Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
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Publication number: 20250063759Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.Type: ApplicationFiled: November 6, 2024Publication date: February 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
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Publication number: 20240147693Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: Byung Yoon Kim, Sheng Wei Yang, Si-Woo Lee, Mark Zaleski
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Patent number: 11903183Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.Type: GrantFiled: October 1, 2020Date of Patent: February 13, 2024Assignee: Micron Technology, Inc.Inventors: Byung Yoon Kim, Sheng Wei Yang, Si-Woo Lee, Mark Zaleski
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Patent number: 11848282Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.Type: GrantFiled: August 16, 2022Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Hyunsuk Chun, Sheng Wei Yang, Shams U. Arifeen
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Patent number: 11616028Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.Type: GrantFiled: October 5, 2020Date of Patent: March 28, 2023Assignee: Micron Technology, Inc.Inventors: Shams U. Arifeen, Hyunsuk Chun, Sheng Wei Yang, Keizo Kawakita
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Publication number: 20230086907Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.Type: ApplicationFiled: August 16, 2022Publication date: March 23, 2023Inventors: Hyunsuk Chun, Sheng Wei Yang, Shams U. Arifeen
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Publication number: 20230014320Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.Type: ApplicationFiled: September 19, 2022Publication date: January 19, 2023Applicant: Micron Technology, Inc.Inventors: Yi Fang Lee, Jaydip Guha, Lars P. Heineck, Kamal M. Karda, Si-Woo Lee, Terrence B. McDaniel, Scott E. Sills, Kevin J. Torek, Sheng-Wei Yang
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Patent number: 11488981Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.Type: GrantFiled: July 21, 2020Date of Patent: November 1, 2022Assignee: Micron Technology, Inc.Inventors: Yi Fang Lee, Jaydip Guha, Lars P. Heineck, Kamal M. Karda, Si-Woo Lee, Terrence B. McDaniel, Scott E. Sills, Kevin J. Torek, Sheng-Wei Yang
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Patent number: 11444037Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.Type: GrantFiled: September 3, 2020Date of Patent: September 13, 2022Assignee: Micron Technology, Inc.Inventors: Hyunsuk Chun, Sheng Wei Yang, Shams U. Arifeen
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Publication number: 20220108988Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.Type: ApplicationFiled: October 1, 2020Publication date: April 7, 2022Inventors: Byung Yoon Kim, Sheng Wei Yang, Si-Woo Lee, Mark Zaleski
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Publication number: 20220028903Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.Type: ApplicationFiled: July 21, 2020Publication date: January 27, 2022Applicant: Micron Technology, Inc.Inventors: Yi Fang Lee, Jaydip Guha, Lars P. Heineck, Kamal M. Karda, Si-Woo Lee, Terrence B. McDaniel, Scott E. Sills, Kevin J. Torek, Sheng-Wei Yang
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Publication number: 20210020585Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.Type: ApplicationFiled: October 5, 2020Publication date: January 21, 2021Inventors: Shams U. Arifeen, Hyunsuk Chun, Sheng Wei Yang, Keizo Kawakita
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Patent number: 10891410Abstract: In an example embodiment, a computer-implemented method is provided for receiving an integrated circuit design, wherein the integrated circuit design comprises at least one position in violation of one or more design rules associated with the integrated design, identifying one or more design patterns at the at least one violating position, generating one or more pattern graphs for the one or more design patterns, extracting a system on chip design for transformation into a block graph, and. comparing the block graph with each of the one or more pattern graphs to determine whether the at least one violating position is cleared. In circumstances where a match is found between the block graph and the each of the one or more pattern graphs, the computer-implemented method further comprises changing the one or more design patterns and repeating the step of comparing until there is no further match found.Type: GrantFiled: July 3, 2019Date of Patent: January 12, 2021Assignee: Synopsys, Inc.Inventors: Chin-Hsiung Hsu, Philip Hui-Yuh Tai, Sheng-Wei Yang, Guo-Ting Wang
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Publication number: 20200402925Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.Type: ApplicationFiled: September 3, 2020Publication date: December 24, 2020Inventors: Hyunsuk Chun, Sheng Wei Yang, Shams U. Arifeen
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Patent number: 10854514Abstract: A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps including forming a plurality of conductive lines having trenches therebetween; forming a contact layer in the trench; and forming a dielectric layer interposed in the contact layer and configured to divide the contact layer into two contacts. The method also comprises removing the dielectric layer to form a space and forming a cap layer over the two contacts to form an air gap therein. The method further comprises forming a second air gap between the conductive line and the two contacts.Type: GrantFiled: April 23, 2019Date of Patent: December 1, 2020Assignee: Micron Technology, Inc.Inventors: Tieh-Chiang Wu, Wen-Chieh Wang, Sheng-Wei Yang