Patents by Inventor Sheng-Wei Yang

Sheng-Wei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12166126
    Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
  • Publication number: 20240395795
    Abstract: A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-I HUANG, Ting-Wei CHIANG, Shih-Chi FU, Sheng-Fang CHENG, Jung-Chan YANG
  • Publication number: 20240384416
    Abstract: A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Yung-Tsun LIU, Kuang-Wei CHENG, Sheng-chun YANG, Chih-Tsung LEE, Chyi-Tsong NI
  • Publication number: 20240387148
    Abstract: A tunable plasma exclusion zone in semiconductor fabrication is provided. A semiconductor wafer is provided within a chamber of a plasma processing apparatus between a first plasma electrode and a second plasma electrode. A plasma is generated from a process gas within the chamber and an electric field between the first plasma electrode and the second plasma electrode. The plasma is at least partially excluded from an edge region of the semiconductor wafer by a plasma exclusion zone (PEZ) ring within the chamber. The plasma may be tuned toward a center of the semiconductor wafer by electrically coupling an electrode ring of the PEZ ring to a voltage potential.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Che Wei Yang, Chih Cheng Shih, Sheng-Chan Li, Cheng-Yuan Tsai, Sheng-Chau Chen
  • Publication number: 20240381630
    Abstract: In some embodiments, the present disclosure relates to a memory device that includes gate electrode layers arranged over a substrate. A first memory cell is arranged over the substrate and includes first and second source/drain conductive lines that extend through the gate electrode layers. A barrier structure is arranged between the first and second source/drain conductive lines. A channel layer is arranged on outermost sidewalls of the first and second source/drain conductive lines. A first dielectric layer is arranged between the barrier structure and the channel layer. A memory layer is arranged on sidewalls of the channel layer. The first dielectric layer has a first maximum width measured between outermost sidewalls of the first dielectric layer. The first source/drain conductive line has a second maximum width measured between the outermost sidewalls of the first source/drain conductive line. The second width is greater than the first width.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Yu-Wei Jiang, Sheng-Chih Lai, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240379721
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. A plurality of photodetectors is disposed in the semiconductor substrate. An isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Sheng-Chan Li, Hau-Yi Hsiao, Che Wei Yang, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Publication number: 20240381651
    Abstract: A semiconductor memory structure includes a ferroelectric layer and a channel layer formed over the ferroelectric layer. The structure also includes a source structure and a drain structure formed over the channel layer. The structure further includes a first isolation structure formed between the source structure and the drain structure. The source structure extends over the cap layer and towards the drain structure.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Hung-Chang Sun, Sheng-Chih Lai, Cheng-Jun Wu, Yu-Wei Jiang, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240354487
    Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fong-yuan CHANG, Chun-Chen CHEN, Sheng-Hsiung CHEN, Ting-Wei CHIANG, Chung-Te LIN, Jung-Chan YANG, Lee-Chung LU, Po-Hsiang HUANG
  • Patent number: 12125839
    Abstract: A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-I Huang, Ting-Wei Chiang, Shih-Chi Fu, Sheng-Fang Cheng, Jung-Chan Yang
  • Publication number: 20240339422
    Abstract: Some implementations described herein provide techniques and apparatuses for forming a stacked die product including two or more integrated circuit dies. A bond interface between two integrated circuit dies that are included in the stacked die product includes a layered structure. As part of the layered structure, respective layers of a sealant material are directly on co-facing surfaces of the two integrated circuit dies. The layered structure further includes one or more bonding layers between the respective layers of the sealant material that are directly on the co-facing surfaces of the two integrated circuit dies. The layered structure may reduce lateral stresses throughout the bond interface to reduce a likelihood of warpage of the two integrated circuit dies.
    Type: Application
    Filed: April 10, 2023
    Publication date: October 10, 2024
    Inventors: Che Wei YANG, Kuo-Ming WU, Sheng-Chau CHEN, Cheng-Yuan TSAI, Hau-Yi HSIAO, Chung-Yi YU
  • Publication number: 20240332163
    Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Inventors: Che Wei YANG, Tsun-Kai TSAO, Sheng-Chau CHEN, Sheng-Chan LI, Cheng-Yuan TSAI
  • Patent number: 12102393
    Abstract: A surgical robotic arm control system and a control method thereof are provided. The surgical robotic arm control system includes a surgical robotic arm, an image capturing unit, and a processor. The surgical robotic arm has multiple joint axes. The image capturing unit obtains a first image. The processor executes a spatial environment recognition module to generate a first environment information image, a first direction information image, and a first depth information image according to the first image. The processor executes a spatial environment image processing module to calculate path information according to the first environment information image, the first direction information image, and the first depth information image. The processor executes a robotic arm motion feedback module to operate the surgical robotic arm to move according to the path information.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: October 1, 2024
    Assignee: Metal Industries Research & Development Centre
    Inventors: Jian Jia Zeng, Bo-Wei Pan, Sheng-Hong Yang
  • Publication number: 20240321848
    Abstract: A package includes a redistribution structure, a bridge die, conductive pillars, connectors, a first die, first solder joints, and second solder joints. The bridge die includes a substrate, a dielectric layer disposed on the substrate, and routing patterns embedded in the dielectric layer. The conductive pillars are coupled to the redistribution structure at a position that is laterally offset from the bridge die. The connectors are coupled to the bridge die and the redistribution structure, such that the bridge die is electrically coupled to the redistribution structure through at least the connectors. The first solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the bridge die. The second solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the conductive pillars.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
  • Publication number: 20240311542
    Abstract: A rectilinear-block placement method includes disposing a first sub-block of each flexible block on a layout area of a chip canvas according to a reference position, generating an edge-depth map relative to first sub-blocks of flexible blocks on the layout area, predicting positions of second sub-blocks of the flexible blocks with depth values on the edge-depth map by a machine learning model, and positioning the second sub-blocks on the layout area according to the predicted positions of the second sub-blocks of the flexible blocks.
    Type: Application
    Filed: December 27, 2023
    Publication date: September 19, 2024
    Applicant: MEDIATEK INC.
    Inventors: Jen-Wei Lee, Yi-Ying Liao, Te-Wei Chen, Kun-Yu Wang, Sheng-Tai Tseng, Ronald Kuo-Hua Ho, Bo-Jiun Hsu, Wei-Hsien Lin, Chun-Chih Yang, Chih-Wei Ko, Tai-Lai Tung
  • Publication number: 20240304426
    Abstract: A radio frequency (RF) screen for a microwave powered ultraviolet (UV) lamp system is disclosed. In one example, a disclosed RF screen includes: a sheet comprising a conductive material; and a frame around edges of the sheet. The conductive material defines a predetermined mesh pattern of individual openings across substantially an operative area of the screen. Each of the individual openings has a triangular shape.
    Type: Application
    Filed: May 17, 2024
    Publication date: September 12, 2024
    Inventors: Sheng-chun YANG, Po-Wei LIANG, Chao-Hung WAN, Yi-Ming LIN, Liu Che KANG
  • Publication number: 20240303408
    Abstract: The application discloses a method and a system for shaping flexible blocks on a chip canvas in an integrated circuit design. An input is received describing geometric features of flexible blocks. A set of flexible blocks are generated based on the input. Obtained block areas of the set of flexible blocks are computed. Whether the set of flexible blocks are legal is determined based on determining whether area differences between the obtained block areas and a plurality of required areas for the set of flexible blocks meet a requirement. The set of flexible blocks are updated until the set of flexible blocks are all legal.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 12, 2024
    Inventors: Kun-Yu WANG, Sheng-Tai TSENG, Yi-Ying LIAO, Jen-Wei LEE, Ronald Kuo-Hua HO, Bo-Jiun HSU, Te-Wei CHEN, Chun-Chih YANG, Tai-Lai TUNG
  • Patent number: 12087522
    Abstract: A backlight module is applied to providing light to a plurality of keyswitches of a keyboard. Each keyswitch has a keycap and an elastic member abutting against the keycap. The backlight module includes a membrane circuit board and a light guide plate. The membrane circuit board has a light emitting diode corresponding to the keyswitch. The light emitting diode is located at a side of the elastic member and emits light to the keycap. The light guide plate is disposed on the membrane circuit board. The light guide plate has a slot hole for containing the light emitting diode and has a hole corresponding to the elastic member. An optical microstructure is formed on the light guide plate for guiding light of the light emitting diode to be incident to the keycap. The elastic member passes through the hole to be disposed on the membrane circuit board.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: September 10, 2024
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Po-Wei Tsai, Yen-Chang Chen, Sheng-Yun Yang
  • Patent number: 12084769
    Abstract: A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Tsun Liu, Kuang-Wei Cheng, Sheng-chun Yang, Chih-Tsung Lee, Chyi-Tsong Ni
  • Patent number: 12087518
    Abstract: A keyboard includes a plurality of keyswitches, a plastic baseplate, and a membrane circuit board. Each keyswitch has a keycap, a lifting mechanism and an elastic member. The lifting mechanism is movably connected to the keycap. The elastic member abuts against the keycap. The plastic baseplate has a first hole formed corresponding to each elastic member and has a connecting structure corresponding to each lifting mechanism. The connecting structure is movably connected to the lifting mechanism to make the keycap movable relative to the plastic baseplate. The membrane circuit board is disposed under the plastic baseplate. Each elastic member passes through the first hole on the plastic baseplate to be disposed on the membrane circuit board. When the keycap is pressed, the elastic member deforms downward to trigger the membrane circuit board. When the keycap is released, the elastic member returns the keycap to its original position.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: September 10, 2024
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Po-Wei Tsai, Sheng-Yun Yang
  • Patent number: 12087517
    Abstract: A keyboard is applied to mounting on a holding baseplate of a computer device and includes a plurality of keyswitches, a membrane circuit board and a baseplate. The membrane circuit board is disposed under the plurality of keyswitches. The baseplate is disposed between the plurality of keyswitches and the membrane circuit board and is connected to the plurality of keyswitches, so as to make the plurality of keyswitches movable relative to the baseplate for triggering the membrane circuit board. The baseplate has a plurality of hooks. The plurality of hooks passes through the membrane circuit board to be engaged with a plurality of engaging hole structures of the holding baseplate respectively, so as to detachably mount the keyboard on the computer device. A number of the plurality of hooks is greater than forty.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: September 10, 2024
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Po-Wei Tsai, Sheng-Yun Yang