Abstract: In some embodiments, the present disclosure relates to a memory device that includes gate electrode layers arranged over a substrate. A first memory cell is arranged over the substrate and includes first and second source/drain conductive lines that extend through the gate electrode layers. A barrier structure is arranged between the first and second source/drain conductive lines. A channel layer is arranged on outermost sidewalls of the first and second source/drain conductive lines. A first dielectric layer is arranged between the barrier structure and the channel layer. A memory layer is arranged on sidewalls of the channel layer. The first dielectric layer has a first maximum width measured between outermost sidewalls of the first dielectric layer. The first source/drain conductive line has a second maximum width measured between the outermost sidewalls of the first source/drain conductive line. The second width is greater than the first width.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.

Abstract: Disclosed is a gripping mechanism including a first bracket, a second bracket, a first guide rod, a third bracket, an actuating module, a gripping block and a gripper. The second bracket is pivotally connected to the first bracket. The first guide rod is fixed on the second bracket. The third bracket is slidably connected to the first guide rod. The actuating module is disposed on the third bracket. The gripping block is slidably disposed on the third bracket, wherein the gripping block is connected to the actuating module. The gripper is fixed on the third bracket, wherein the actuating module is located between the first guide rod and the gripping block, and the gripping block is located between the actuating module and the gripper. A mobile robot is also disclosed.

Abstract: Disclosed is a gripping mechanism including a first bracket, a second bracket, a first guide rod, a third bracket, an actuating module, a gripping block and two grippers. The second bracket is connected to the first bracket. The third bracket is connected to the second bracket. The actuating module is disposed on the third bracket. The gripping block is slidably disposed on the third bracket and is connected to the actuating module. The two grippers are fixed on the terminal end of the third bracket distal from the first bracket and the second bracket, wherein the gripping block is located between the actuating module and the two grippers and the actuating module is adapted to drive the gripping block to slide close to or slide away from the two grippers. A mobile robot is also disclosed.

Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.

Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.

Abstract: A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.

Abstract: A tunable plasma exclusion zone in semiconductor fabrication is provided. A semiconductor wafer is provided within a chamber of a plasma processing apparatus between a first plasma electrode and a second plasma electrode. A plasma is generated from a process gas within the chamber and an electric field between the first plasma electrode and the second plasma electrode. The plasma is at least partially excluded from an edge region of the semiconductor wafer by a plasma exclusion zone (PEZ) ring within the chamber. The plasma may be tuned toward a center of the semiconductor wafer by electrically coupling an electrode ring of the PEZ ring to a voltage potential.

Abstract: A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. A plurality of photodetectors is disposed in the semiconductor substrate. An isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.

Abstract: A semiconductor memory structure includes a ferroelectric layer and a channel layer formed over the ferroelectric layer. The structure also includes a source structure and a drain structure formed over the channel layer. The structure further includes a first isolation structure formed between the source structure and the drain structure. The source structure extends over the cap layer and towards the drain structure.

Abstract: In some embodiments, the present disclosure relates to a memory device that includes gate electrode layers arranged over a substrate. A first memory cell is arranged over the substrate and includes first and second source/drain conductive lines that extend through the gate electrode layers. A barrier structure is arranged between the first and second source/drain conductive lines. A channel layer is arranged on outermost sidewalls of the first and second source/drain conductive lines. A first dielectric layer is arranged between the barrier structure and the channel layer. A memory layer is arranged on sidewalls of the channel layer. The first dielectric layer has a first maximum width measured between outermost sidewalls of the first dielectric layer. The first source/drain conductive line has a second maximum width measured between the outermost sidewalls of the first source/drain conductive line. The second width is greater than the first width.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.

Abstract: Some implementations described herein provide techniques and apparatuses for forming a stacked die product including two or more integrated circuit dies. A bond interface between two integrated circuit dies that are included in the stacked die product includes a layered structure. As part of the layered structure, respective layers of a sealant material are directly on co-facing surfaces of the two integrated circuit dies. The layered structure further includes one or more bonding layers between the respective layers of the sealant material that are directly on the co-facing surfaces of the two integrated circuit dies. The layered structure may reduce lateral stresses throughout the bond interface to reduce a likelihood of warpage of the two integrated circuit dies.

Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.

Abstract: A surgical robotic arm control system and a control method thereof are provided. The surgical robotic arm control system includes a surgical robotic arm, an image capturing unit, and a processor. The surgical robotic arm has multiple joint axes. The image capturing unit obtains a first image. The processor executes a spatial environment recognition module to generate a first environment information image, a first direction information image, and a first depth information image according to the first image. The processor executes a spatial environment image processing module to calculate path information according to the first environment information image, the first direction information image, and the first depth information image. The processor executes a robotic arm motion feedback module to operate the surgical robotic arm to move according to the path information.

Abstract: A package includes a redistribution structure, a bridge die, conductive pillars, connectors, a first die, first solder joints, and second solder joints. The bridge die includes a substrate, a dielectric layer disposed on the substrate, and routing patterns embedded in the dielectric layer. The conductive pillars are coupled to the redistribution structure at a position that is laterally offset from the bridge die. The connectors are coupled to the bridge die and the redistribution structure, such that the bridge die is electrically coupled to the redistribution structure through at least the connectors. The first solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the bridge die. The second solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the conductive pillars.

Abstract: A rectilinear-block placement method includes disposing a first sub-block of each flexible block on a layout area of a chip canvas according to a reference position, generating an edge-depth map relative to first sub-blocks of flexible blocks on the layout area, predicting positions of second sub-blocks of the flexible blocks with depth values on the edge-depth map by a machine learning model, and positioning the second sub-blocks on the layout area according to the predicted positions of the second sub-blocks of the flexible blocks.

Abstract: A radio frequency (RF) screen for a microwave powered ultraviolet (UV) lamp system is disclosed. In one example, a disclosed RF screen includes: a sheet comprising a conductive material; and a frame around edges of the sheet. The conductive material defines a predetermined mesh pattern of individual openings across substantially an operative area of the screen. Each of the individual openings has a triangular shape.