Abstract: The present disclosure provides an array substrate, a method for preparing the same, and a display device. The method includes: forming a metal layer on a base substrate; coating a photoresist on the metal layer; exposing the photoresist by a mask plate in such a manner that an amount of light acting on a first photoresist portion is less than that of light acting on a second photoresist portion to form a first photoresist reserved portion located and a second photoresist reserved portion located; after etching off the metal portion, stripping the first photoresist reserved portion and the second photoresist reserved portion, to obtain the first metal pattern located in the fan-out area and the second metal pattern located in the display area, in which a period size of the first metal pattern being smaller than a period size of the second metal pattern.

Abstract: Disclosed are a display substrate, a display device, a manufacturing method and a repairing method. A capacitor structure in the display substrate includes a first electrode and a second electrode. The first electrode includes a first main body portion extending in a first direction, first branch portions extending in a second direction, and a first connection portion connecting the first branch portions to the first main body portion. The second electrode includes a second main body portion extending in the first direction, second branch portions extending in the second direction, and a second connection portion connecting the second branch portions to the second main body portion. One side of the first electrode having the first branch portions faces one side of the second electrode having the second branch portions, and each first branch portion and a corresponding second branch portion form a capacitor.

Abstract: A pixel structure and a manufacturing method thereof, an array substrate and a display device are provided. The pixel structure includes: a signal line; a common electrode line an extension direction of which is same as an extension direction of the signal line; a transistor including a semiconductor layer which includes a source region and a drain region; a first storage electrode which is insulated from the common electrode line and is connected with the drain region of the semiconductor layer; and a second storage electrode which is connected with the common electrode line and is insulated from the first storage electrode. In the pixel structure, portions, between the signal line and the common electrode line, of the first storage electrode and the second storage electrode includes overlap with each other to form a first storage capacitance.

Abstract: Disclosed are a display substrate, a display device, a manufacturing method and a repairing method. A capacitor structure in the display substrate includes a first electrode and a second electrode. The first electrode includes a first main body portion extending in a first direction, first branch portions extending in a second direction, and a first connection portion connecting the first branch portions to the first main body portion. The second electrode includes a second main body portion extending in the first direction, second branch portions extending in the second direction, and a second connection portion connecting the second branch portions to the second main body portion. One side of the first electrode having the first branch portions faces one side of the second electrode having the second branch portions, and each first branch portion and a corresponding second branch portion form a capacitor.

Abstract: The present disclosure provides an array substrate, a method for preparing the same, and a display device. The method includes: forming a metal layer on a base substrate; coating a photoresist on the metal layer; exposing the photoresist by a mask plate in such a manner that an amount of light acting on a first photoresist portion is less than that of light acting on a second photoresist portion to form a first photoresist reserved portion located and a second photoresist reserved portion located; after etching off the metal portion, stripping the first photoresist reserved portion and the second photoresist reserved portion, to obtain the first metal pattern located in the fan-out area and the second metal pattern located in the display area, in which a period size of the first metal pattern being smaller than a period size of the second metal pattern.

Abstract: The present application discloses a first display substrate including a plurality of core-coil assemblies configured to detect a touch. Each of the plurality of core-coil assemblies includes a first base substrate; a core layer on the first base substrate and including a plurality of magnetic permeable cores substantially along a first direction and spaced apart from each other, each of the plurality of magnetic permeable cores substantially along a second direction; and a conductive coil wound around the plurality of magnetic permeable cores for multiple turns and insulated from the core layer.

Abstract: The present application discloses a first display substrate including a plurality of core-coil assemblies configured to detect a touch. Each of the plurality of core-coil assemblies includes a first base substrate; a core layer on the first base substrate and including a plurality of magnetic permeable cores substantially along a first direction and spaced apart from each other, each of the plurality of magnetic permeable cores substantially along a second direction; and a conductive coil wound around the plurality of magnetic permeable cores for multiple turns and insulated from the core layer.

Abstract: An array substrate includes a display region and a peripheral circuit region surrounding the display region. The array substrate further includes: a base substrate; first TFTs arranged on a first surface of the base substrate and at the display region, and each first TFT including a first gate electrode, a first active layer and a first source-drain electrode; and second TFTs arranged on the first surface and at the peripheral circuit region, and each second TFT including a second gate electrode, a second active layer and a second source-drain electrode. The first active layer of each first TFT is made of a material different from, and arranged at a same layer as, the second active layer of each second TFT, and the first source-drain electrode is arranged at a same layer as the second source-drain electrode.

Abstract: A pixel structure and a manufacturing method thereof, an array substrate and a display device are provided. The pixel structure includes: a signal line; a common electrode line an extension direction of which is same as an extension direction of the signal line; a transistor including a semiconductor layer which includes a source region and a drain region; a first storage electrode which is insulated from the common electrode line and is connected with the drain region of the semiconductor layer; and a second storage electrode which is connected with the common electrode line and is insulated from the first storage electrode. In the pixel structure, portions, between the signal line and the common electrode line, of the first storage electrode and the second storage electrode includes overlap with each other to form a first storage capacitance.

Abstract: The present disclosure provides an array substrate, its driving method and manufacturing method, and a display device. The array substrate includes a transistor layer arranged on a base, and a first transparent conductive layer, a first insulation layer, a second transparent conductive layer, a second insulation layer and a third transparent conductive layer sequentially arranged on the transistor layer. The first transparent conductive layer covers the transistor layer at a display area, the second transparent conductive layer includes a pattern of touch electrodes, and the third transparent conductive layer includes a pattern of pixel electrodes. Within any pixel area of the display area, the pixel electrode is connected to a pixel electrode connection end of the transistor layer through a via-hole in the first insulation layer and the second insulation layer, and the first transparent conductive layer is provided with an opening at a position corresponding to the via-hole.

Abstract: An array substrate includes a display region and a peripheral circuit region surrounding the display region. The array substrate further includes: a base substrate; first TFTs arranged on a first surface of the base substrate and at the display region, and each first TFT including a first gate electrode, a first active layer and a first source-drain electrode; and second TFTs arranged on the first surface and at the peripheral circuit region, and each second TFT including a second gate electrode, a second active layer and a second source-drain electrode. The first active layer of each first TFT is made of a material different from, and arranged at a same layer as, the second active layer of each second TFT, and the first source-drain electrode is arranged at a same layer as the second source-drain electrode.

Abstract: The present application discloses a method of fabricating a thin film transistor, including forming a semiconductor layer having a pattern corresponding to that of the active layer on a base substrate; forming a first photoresist layer on a side of the semiconductor layer distal to the base substrate; the first photoresist layer being in an area corresponding to the channel region, the second doped region, and the fourth doped region; doping a region of the semiconductor layer corresponding to the first doped region and the third doped region using the first photoresist layer as a mask plate; forming a second photoresist layer by removing a portion of the first photoresist layer to expose an initial portion of the semiconductor layer corresponding to at least a portion of the second doped region and at least a portion of the fourth doped region; and doping the initial portion of the semiconductor layer using the second photoresist layer as a mask plate.

Abstract: Preparation method for a thin film transistor, preparation method for an array substrate, an array substrate, and a display apparatus are provided. The preparation method for a thin film transistor includes: forming, on a pattern of a semiconductor layer, a first photoresist pattern including a photoresist with two different thicknesses, and performing a heavily-doped ion implantation process on the pattern of the semiconductor layer by using the first photoresist pattern as a barrier mask; ashing the first photoresist pattern to remove the photoresist with a second thickness and to thin the photoresist with a first thickness, so as to form a second photoresist pattern; and performing a lightly-doped ion implantation process on the pattern of the semiconductor layer by using the second photoresist pattern as a barrier mask.

Abstract: The present application discloses a method of fabricating a thin film transistor, including forming a semiconductor layer having a pattern corresponding to that of the active layer on a base substrate; forming a first photoresist layer on a side of the semiconductor layer distal to the base substrate; the first photoresist layer being in an area corresponding to the channel region, the second doped region, and the fourth doped region; doping a region of the semiconductor layer corresponding to the first doped region and the third doped region using the first photoresist layer as a mask plate; forming a second photoresist layer by removing a portion of the first photoresist layer to expose an initial portion of the semiconductor layer corresponding to at least a portion of the second doped region and at least a portion of the fourth doped region; and doping the initial portion of the semiconductor layer using the second photoresist layer as a mask plate.

Abstract: Preparation method for a thin film transistor, preparation method for an array substrate, an array substrate, and a display apparatus are provided. The preparation method for a thin film transistor includes: forming, on a pattern of a semiconductor layer, a first photoresist pattern including a photoresist with two different thicknesses, and performing a heavily-doped ion implantation process on the pattern of the semiconductor layer by using the first photoresist pattern as a barrier mask; ashing the first photoresist pattern to remove the photoresist with a second thickness and to thin the photoresist with a first thickness, so as to form a second photoresist pattern; and performing a lightly-doped ion implantation process on the pattern of the semiconductor layer by using the second photoresist pattern as a barrier mask.

Abstract: The present disclosure provides an array substrate, its driving method and manufacturing method, and a display device. The array substrate includes a transistor layer arranged on a base, and a first transparent conductive layer, a first insulation layer, a second transparent conductive layer, a second insulation layer and a third transparent conductive layer sequentially arranged on the transistor layer. The first transparent conductive layer covers the transistor layer at a display area, the second transparent conductive layer includes a pattern of touch electrodes, and the third transparent conductive layer includes a pattern of pixel electrodes. Within any pixel area of the display area, the pixel electrode is connected to a pixel electrode connection end of the transistor layer through a via-hole in the first insulation layer and the second insulation layer, and the first transparent conductive layer is provided with an opening at a position corresponding to the via-hole.