Abstract: A SerDes module clock network architecture comprises, a reference clock input port, a plurality of data transmission channels, several user logic interfaces, several frequency division branches and a phase locked loop. The reference lock input port receives an input clock and conveys the input clock to the phase locked loop, the phase locked loop receives the input lock and outputs a PLL output clock signal, the PLL output clock signal is conveyed to the plurality of data transmission channels, and the PLL output clock signal is conveyed to the frequency division branches, and after frequency division, user interface clocks are output and conveyed to the user logic interfaces. When the PLL output clock signal in a SerDes is provided to an internal dedicated channel, several frequency division branches are also divided, and after frequency division, the signal is output to the user logic interfaces for use by an FPGA.

Abstract: A processing method for a FIFO memory. The FIFO memory comprises a data caching module and an address control module. The processing method comprises: an address control module receives an empty/full state signal of a data caching module (S200); and the address control module adjusts the read-write address difference of the data caching module (S300).

Abstract: A SerDes module clock network architecture comprises, a reference clock input port, a plurality of data transmission channels, several user logic interfaces, several frequency division branches and a phase locked loop. The reference lock input port receives an input clock and conveys the input clock to the phase locked loop, the phase locked loop receives the input lock and outputs a PLL output clock signal, the PLL output clock signal is conveyed to the plurality of data transmission channels, and the PLL output clock signal is conveyed to the frequency division branches, and after frequency division, user interface clocks are output and conveyed to the user logic interfaces. When the PLL output clock signal in a SerDes is provided to an internal dedicated channel, several frequency division branches are also divided, and after frequency division, the signal is output to the user logic interfaces for use by an FPGA.

Abstract: A method for improving synchro precision of data transmission and system thereof are disclosed. The method includes the following steps: RRU receives a data frame and buffers; frame-parses to a wireless frame impulse signal and a carrier wave data signal of the data frame, setting the maximum time-lapse compensating time; a time-lapse is redeemed to the wireless frame impulse signal after parsing, according to the time of transmission and buffering, and the maximum time-lapse compensating time, and then sends to the communication port of RRU to transmit; a time-lapse is redeemed to the carrier wave data signal after parsing, according to the time of transmission and buffering, the maximum time-lapse compensating time, and transmission time of processing data, the carrier wave data is processed, and then is sent to the communication port of RRU to transmit; the wireless frame impulse signal and the carrier wave data signal are sent to the communication port of RRU simultaneously.