Patents by Inventor Sher Jiun Fang

Sher Jiun Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10944437
    Abstract: We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption. One multiband receiver comprises a first band path comprising a first passive mixer configured to receive a first input RF signal having a first frequency and to be driven by a first local oscillator signal having a frequency about ? the first frequency; a second band path comprising a second passive mixer configured to receive a second input RF signal having a second frequency and to be driven by a second local oscillator signal having a frequency about ? the second frequency; and a base band path comprising a third passive mixer configured to receive intermediate RF signals during a duty cycle and to be driven by a third local oscillator signal having a frequency about ? the first frequency or about ? the second frequency during the duty cycle.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 9, 2021
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Abdellatif Bellaouar, Sher Jiun Fang, Frank Zhang
  • Patent number: 10747254
    Abstract: The disclosure provides a circuit structure including a current source including at least one FDSOI transistor having a back-gate terminal, wherein the current source generates a current proportionate to an absolute temperature of the circuit structure; a first current mirror electrically coupled to the current source and a gate terminal of a device transistor, wherein the first current mirror applies a gate bias to the device transistor based on a magnitude of the current, and wherein a source or drain terminal of the device transistor includes an output current of the circuit structure; and an adjustable voltage source coupled to the back-gate terminal of the at least one FDSOI transistor of the current source, wherein the adjustable voltage source applies a selected back-gate bias voltage to the back-gate terminal of the at least one FDSOI transistor to adjust the current to compensate for process variations of the device transistor.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 18, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sher Jiun Fang, See Taur Lee
  • Publication number: 20200228149
    Abstract: We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption. One multiband receiver comprises a first band path comprising a first passive mixer configured to receive a first input RF signal having a first frequency and to be driven by a first local oscillator signal having a frequency about ? the first frequency; a second band path comprising a second passive mixer configured to receive a second input RF signal having a second frequency and to be driven by a second local oscillator signal having a frequency about ? the second frequency; and a base band path comprising a third passive mixer configured to receive intermediate RF signals during a duty cycle and to be driven by a third local oscillator signal having a frequency about ? the first frequency or about ? the second frequency during the duty cycle.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Abdellatif Bellaouar, Sher Jiun Fang, Frank Zhang
  • Publication number: 20190312603
    Abstract: We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption. One multiband receiver comprises a first band path comprising a first passive mixer configured to receive a first input RF signal having a first frequency and to be driven by a first local oscillator signal having a frequency about ? the first frequency; a second band path comprising a second passive mixer configured to receive a second input RF signal having a second frequency and to be driven by a second local oscillator signal having a frequency about ? the second frequency; and a base band path comprising a third passive mixer configured to receive intermediate RF signals during a duty cycle and to be driven by a third local oscillator signal having a frequency about ? the first frequency or about ? the second frequency during the duty cycle.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 10, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Abdellatif Bellaouar, Sher Jiun Fang, Frank Zhang
  • Patent number: 9774302
    Abstract: Disclosed is an amplifier circuit having a single-ended input and differential outputs. The differential outputs are achieved using a first output branch and a second output branch, each including a common source FET (CS-FET) and a common gate FET (CG-FET) connected in series between ground and a corresponding out node connected to a load. An input signal is applied to the CS-FET in the first output branch and an intermediate signal at an intermediate node between the CS-FET and the CG-FET in the first output branch is applied to the CS-FET in the second output branch. The CG-FET in the first output branch and the CS-FET in the second output branch are equal in size such that their transconductances are approximately equal, such that currents in the two output branches are inverted and the outputs at the output nodes of the two output branches are differential outputs.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: September 26, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Abdellatif Bellaouar, Sher Jiun Fang
  • Patent number: 9413315
    Abstract: In one embodiment, a WCDMA FDD system includes an embedded filter that provides a complex load to transistors in a low noise amplifier. The complex load can be constructed using passive and/or active devices and creates an arbitrary transfer function that supports selective Q-enhancement of poles or zeros. One particular implementation of the embedded filter is in the form of an LC tank circuit. The LC tank circuit is operably coupled to the output of the low noise amplifier and creates a transfer function whose poles and zeros can be selected to reject transmitter leakage in the WCDMA system, while maintain a desirable gain at the frequency of operation.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: August 9, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sher Jiun Fang, Khurram Muhammad
  • Publication number: 20160173145
    Abstract: A variable-gain, low noise amplifier system includes a variable-gain, low noise amplifier, having a matching stage, coupled to an input signal with a plurality of different carrier frequencies, that provides complementary output signals containing the plurality of different carrier frequencies. The variable-gain, low noise amplifier also includes a set of carrier gain control stages, coupled to the complementary output signals, wherein each carrier gain control stage provides an independent gain for one carrier frequency of the plurality of different carrier frequencies. The variable-gain, low noise amplifier system also includes a gain controller, coupled to the variable-gain, low noise amplifier that provides gain control signals to determine the independent gain for each carrier gain control stage. A method of operating a variable-gain, low noise amplifier is also provided.
    Type: Application
    Filed: August 28, 2015
    Publication date: June 16, 2016
    Inventors: Travis Forbes, Abdellatif Bellaouar, Sherif Abdelhalem, Sher Jiun Fang, Frank Zhang
  • Patent number: 8836434
    Abstract: A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: September 16, 2014
    Assignee: Icera Inc.
    Inventors: Abdellatif Bellaouar, Ahmed R. Fridi, Sher Jiun Fang, Hamid Safiri
  • Patent number: 8724736
    Abstract: A transmitter architecture having a single signal path or hardware to cover WCDMA/EDGE/GSM applications, and requires no SAW at the transmitter outputs. The transmitter architecture allows for a transmit convergence feature. A passive mixer with unique driver and furthermore using native devices available from the CMOS process for the mixer cores enables low voltage and low power design, low output noise and high linearity. A digital variable gain amplifier has the capability to cover wide output dynamic range operated from low supply voltage and interfaced digitally with the baseband circuit without DAC. A single transformer is used to combine the outputs from the WCDMA/EDGE and GSM drivers and subsequently convert the differential signal paths into a single-ended signal. RF switches are used to divert the output from the transformer to different bands and applications.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: May 13, 2014
    Assignee: Icera, Inc.
    Inventors: Abdellatif Bellaouar, See Taur Lee, Sher Jiun Fang, Sherif H. K. Embabi, Tajinder Manku
  • Publication number: 20110249770
    Abstract: A transmitter architecture having a single signal path or hardware to cover WCDMA/EDGE/GSM applications, and requires no SAW at the transmitter outputs. The transmitter architecture allows for a transmit convergence feature. A passive mixer with unique driver and furthermore using native devices available from the CMOS process for the mixer cores enables low voltage and low power design, low output noise and high linearity. A digital variable gain amplifier has the capability to cover wide output dynamic range operated from low supply voltage and interfaced digitally with the baseband circuit without DAC. A single transformer is used to combine the outputs from the WCDMA/EDGE and GSM drivers and subsequently convert the differential signal paths into a single-ended signal. RF switches are used to divert the output from the transformer to different bands and applications.
    Type: Application
    Filed: September 8, 2009
    Publication date: October 13, 2011
    Applicant: ICERA INC.
    Inventors: Abdellatif Bellaouar, See Taur Lee, Sher Jiun Fang, Sherif H.K. Embabi, Tajinder Manku
  • Publication number: 20110163815
    Abstract: A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.
    Type: Application
    Filed: September 8, 2009
    Publication date: July 7, 2011
    Applicant: ICERA INC.
    Inventors: Abdellatif Bellaouar, Ahmed R. Fridi, Sher Jiun Fang, Hamid Safiri
  • Publication number: 20080079497
    Abstract: In one embodiment, a WCDMA FDD system includes an embedded filter that provides a complex load to transistors in a low noise amplifier. The complex load can be constructed using passive and/or active devices and creates an arbitrary transfer function that supports selective Q-enhancement of poles or zeros. One particular implementation of the embedded filter is in the form of an LC tank circuit. The LC tank circuit is operably coupled to the output of the low noise amplifier and creates a transfer function whose poles and zeros can be selected to reject transmitter leakage in the WCDMA system, while maintain a desirable gain at the frequency of operation.
    Type: Application
    Filed: August 31, 2006
    Publication date: April 3, 2008
    Inventors: Sher Jiun Fang, Khurram Muhammad
  • Publication number: 20040036541
    Abstract: A wideband digital quadrature local oscillator (LO) generator (300) using clocked-CMOS (C2MOS) latches (302, 304) can operate at very high frequencies, while consuming less current and having lower phase noise as compared to prior art quadrature LO generators using Source-coupled logic (SCL) latches. In addition, the LO generator (300) has no low frequency limit and can output rail-to-rail square waves.
    Type: Application
    Filed: August 26, 2002
    Publication date: February 26, 2004
    Inventors: Sher Jiun Fang, See Taur Lee, Abdellatif Bellaouar
  • Patent number: 6121809
    Abstract: A differential phase splitter circuit for producing opposite phase signals from an input AC signal is provided. A first and second transistor is provided. The source of these transistors are connected to a common first node. Further, these transistors act as a differential amplifier. The gate of the first transistor receives an input AC signal. The drain of the first transistor produces a first output AC signal. Similarly, the drain of the second transistor produces a second output AC signal that is 180 degrees out of phase with the first output AC signal. A source resistor is provided, connected in series to the common first node and ground. Lastly, an LCR feedback circuit is provided. This feedback circuit is connected between the drain of the first transistor and the gate of the second transistor. The LCR feedback circuit couples at least a fraction of the amplitude of the first output AC signal to the gate of the second transistor for amplitude balancing and phase balancing.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: September 19, 2000
    Assignee: Institute of Microelectronics
    Inventors: Huainan Ma, Sher Jiun Fang, Fujiang Lin