Patents by Inventor Sheree Chou

Sheree Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory array with fast bit line precharge
    Patent number: 7082069
    Abstract: An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Precharge transistors are coupled to respective bit lines in the array, and adapted to precharge voltage on the respective bit lines to near a target level. A detector has an input coupled to the reference bit line and an output coupled to the precharge transistors on the plurality of bit lines. The detector generates a precharge signal which turns off the precharge transistors when the reference bit line has a voltage near the target level, and turns on the precharge transistors when the reference bit line has a voltage below the target level.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: July 25, 2006
    Assignee: Macronix International Co., LTD.
    Inventors: Sheree Chou, Lung-Feng Lin, Yu-Shen Lin
  • Memory array with low power bit line precharge
    Patent number: 7082061
    Abstract: An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Clamp transistors are coupled to respective bit lines in the array, and adapted to prevent voltage on the respective bit lines from exceeding a target level. A comparator has an input coupled to the reference bit line and an output coupled to the clamp transistors on the plurality of bit lines. The comparator generates a bias voltage which turns on the clamp transistors at a first bias level when the reference bit line has a voltage below the target level, and a second bias level, which is lower than the first bias level, when the reference bit line has a voltage near the target level.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: July 25, 2006
    Assignee: Macronix International Co., Ltd.
    Inventors: Sheree Chou, Lung-Yi Chueh, Yu-Shen Lin
  • MEMORY ARRAY WITH LOW POWER BIT LINE PRECHARGE
    Publication number: 20060120174
    Abstract: An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Clamp transistors are coupled to respective bit lines in the array, and adapted to prevent voltage on the respective bit lines from exceeding a target level. A comparator has an input coupled to the reference bit line and an output coupled to the clamp transistors on the plurality of bit lines. The comparator generates a bias voltage which turns on the clamp transistors at a first bias level when the reference bit line has a voltage below the target level, and a second bias level, which is lower than the first bias level, when the reference bit line has a voltage near the target level.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 8, 2006
    Applicant: Macronix International Co., Ltd
    Inventors: Sheree Chou, Lung-Yi Chueh, Yu-Shen Lin
  • MEMORY ARRAY WITH FAST BIT LINE PRECHARGE
    Publication number: 20060120175
    Abstract: An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Precharge transistors are coupled to respective bit lines in the array, and adapted to precharge voltage on the respective bit lines to near a target level. A detector has an input coupled to the reference bit line and an output coupled to the precharge transistors on the plurality of bit lines. The detector generates a precharge signal which turns off the precharge transistors when the reference bit line has a voltage near the target level, and turns on the precharge transistors when the reference bit line has a voltage below the target level.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 8, 2006
    Applicant: Macronix International Co., Ltd.
    Inventors: Sheree Chou, Yung-Feng Lin, Yu-Shen Lin