Patents by Inventor Shereen ELHALAWATY

Shereen ELHALAWATY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thermally-optimized tunable stack in cavity package-on-package
    Patent number: 11769753
    Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: September 26, 2023
    Assignee: Intel Corporation
    Inventors: George Vakanas, Aastha Uppal, Shereen Elhalawaty, Aaron McCann, Edvin Cetegen, Tannaz Harirchian, Saikumar Jayaraman
  • THERMALLY-OPTIMIZED TUNABLE STACK IN CAVITY PACKAGE-ON-PACKAGE
    Publication number: 20200043894
    Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Inventors: George VAKANAS, Aastha UPPAL, Shereen ELHALAWATY, Aaron MCCANN, Edvin CETEGEN, Tannaz HARIRCHIAN, Saikumar JAYARAMAN