Abstract: In a switched capacitor type digital-to-analog (D/A) converter, a group of n bits of the binary word are applied to n parallel branches of the D/A converter, respectively. In a given branch, the corresponding bit is applied to a control terminal of a corresponding switch associated with a corresponding switched capacitor. Depending on the logic level of the bit, the switched capacitor is charged to a reference voltage or remains discharged. Then, the switched capacitor of the given branch is coupled by a transfer switch in parallel with a summing capacitor to provide for charge redistribution. The capacitances of the switched capacitor and of the summing capacitor are equal. The time allocated for either discharging the switched capacitor or charge redistribution is made shorter than the time allocated for charging the capacitor. Charging/discharging the capacitor is accomplished via a common transistor.

Abstract: A video display driver applies a video signal to column electrodes of a liquid crystal display. The display driver includes a reference ramp generator and column data line drivers. A reference ramp signal is combined with the video signal and applied to an input of a comparator. The comparator controls a first transistor that couples a data ramp signal to a given column of pixels. The first transistor at least partially initializes a voltage developed in the given column of pixels prior to an instant when the data ramp signal begins upramping. A second transistor that is coupled in parallel with the first transistor insures that the column voltage is fully initialized.

Abstract: A video display driver applies a video signal to pixels arranged in columns and rows of a liquid crystal display. A given column or data line driver includes a field effect transistor that operates as a comparator. The comparator is responsive to the video signal and to a reference ramp signal. A triggering voltage of the comparator is automatically and periodically adjusted. A drain voltage of the transistor that is equal to a threshold voltage of the transistor is developed in a stray capacitance, during the automatic adjustment period. A pulse signal, is coupled via the capacitance to increase the drain voltage. The drain voltage is applied to a gate electrode of a second field effect transistor that applies a data ramp voltage to the pixels. The pulse signal provides a small amount of drive in the second transistor.

Abstract: A liquid crystal display includes pixels that are arranged in columns and rows. Data line drivers responsive to a video signal develop output signals in data lines that correspond with the columns, respectively. An adjustment data line driver is provided. The adjustment data line driver is responsive to a reference DC constant signal at a mid-range of the video signal. An output signal of the adjustment data line driver is coupled to the other data line drivers in a negative feedback manner to compensate for output signal variations in the other data line drivers.

Abstract: A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. The input transistor switch charges a capacitance associated with a control electrode of a switched pull-up output transistor. The voltage in the capacitance conditions the output transistor for generating an output pulse when subsequently a clock signal occurs to the output transistor. A clamping transistor discharges the capacitance in a manner to prevent further generation of the output pulse when subsequent pulses of the clock signal occur. The clamping transistor is responsive to an output pulse of a stage downstream in the chain. An impedance that is developed at the control electrode is substantially higher after the clamping operation occurs and remain high for most of the vertical interval.

Abstract: A select line scanner for a liquid crystal display includes a plurality of cascaded stages each having an input terminal and an output terminal. Each stage includes a push-pull output circuit including pull up and pull down transistors driven with separate control signals. A further transistor has its conduction path coupled between the control electrode and a point of potential of sufficient value to turn the pull up transistor off. The control electrode of the further transistor is coupled to an output of a succeeding one of the cascaded stages to insure that the output of the respective stage cannot drift to an on state.

Abstract: A set of N digital data bits serially supplied to an input node are converted to an analog voltage by means of N binary weighted capacitors and N switching transistors, one capacitor being associated with one switching transistor for each one of the N digital data bits. Each capacitor is connected between an output node and via the conduction path of its associated switching transistor to a first power terminal. Two transistors are used to selectively sample the N bits of serial data and to couple and store the sampled data on the gates of the switching transistors which are precharged so that the two transistors coupling the serial data only need to conduct in the common source mode. The serial data applied to the gates of the switching transistor is transferred to the N capacitors when a charging voltage is applied to the output node.

Abstract: A triangular waveform generator for applying a scanning waveform to the scan electrodes of a modular display device includes a constant current source and a coupling transformer. A charge storage capacitor is coupled to the secondary of the coupling transformer. A squarewave generator actuates a switch to alternately charge the capacitor in opposite directions resulting in the generation of the triangular waveform. Discharge means is provided to protect the switch from high voltages which could be developed when the generator is turned off.

Abstract: A horizontal sync signal simultaneously addresses a second counter and a first memory addressing circuit comprising a frequency multiplier connected to a first counter. The output of the first counter addresses the first memory. A comparator compares the outputs from the first memory and the second counter, and generates an output which may be compensated if necessary to subsequently assure proper sequencing of the display device. The comparator output addresses a second memory. Outputs from the second memory and the second counter are combined in an adder and the summation thereof are fed into a subtractor along with the output of the first memory. The output of the subtractor is fed into a binary-to-decimal converter which in turn feeds a row electrode driver circuit.

Abstract: An apparatus for measuring the current-voltage characteristics of a TRAPATT diode to determine its operational performance prior to mounting in its intended circuit. The apparatus comprises a pulse generator for generating a pulsed signal which is modulated by a modulator such that the current of the pulsed signal as applied to the diode periodically increases and decreases. The modulating signal is generated by a full wave bridge rectifier. The modulated signal sweeps the current applied to the diode through the characteristic curve of the diode triggering the diode into the TRAPATT mode of operation. An indicator such as an oscilloscope coupled to the diode displays the characteristic curve including the negative resistance region of the diode occurring during TRAPATT operation.