Patents by Inventor Shesh Mani Pandey

Shesh Mani Pandey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190273148
    Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 5, 2019
    Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
  • Patent number: 10403742
    Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 3, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
  • Patent number: 10361289
    Abstract: A method of thermally oxidizing a Si fin to form an oxide layer over the Si fin and then forming an ALD oxide layer over the oxide layer and resulting device are provided. Embodiments include forming a plurality of Si fins on a Si substrate; forming a dielectric layer over the plurality of Si fins and the Si substrate; recessing the dielectric layer, exposing a top portion of the plurality of Si fins; thermally oxidizing surface of the top portion of the plurality of Si fins, an oxide layer formed; and forming an ALD oxide layer over the oxide layer.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Zhao, Shahab Siddiqui, Haiting Wang, Ting-Hsiang Hung, Yiheng Xu, Beth Baumert, Jinping Liu, Scott Beasor, Yue Zhong, Shesh Mani Pandey
  • Patent number: 10355104
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yi Qi, Sang Woo Lim, Kyung-Bum Koo, Alina Vinslava, Pei Zhao, Zhenyu Hu, Hsien-Ching Lo, Joseph F. Shepard, Jr., Shesh Mani Pandey
  • Patent number: 10347748
    Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, forming a gate structure around the fin and, after forming the gate structure, forming a final source/drain cavity in the fin, wherein the source/drain cavity includes an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of the gate structure, and wherein the lower innermost edge extends laterally further under the gate structure than does the upper innermost edge. The method also includes performing an epitaxial growth process to form an epi semiconductor material in the final source/drain cavity.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shesh Mani Pandey, Muhammad Rahman, Srikanth Balaji Samavedam
  • Publication number: 20190131432
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 2, 2019
    Inventors: Yi Qi, Sang Woo Lim, Kyung-Bum Koo, Alina Vinslava, Pei Zhao, Zhenyu Hu, Hsien-Ching Lo, Joseph F. Shepard, JR., Shesh Mani Pandey
  • Publication number: 20190097019
    Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 28, 2019
    Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
  • Publication number: 20190088766
    Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial sidewall spacer adjacent a sidewall spacer of a transistor and, with the sacrificial sidewall spacer in position, forming openings in an active layer of an SOI substrate adjacent the sacrificial sidewall spacer so as to thereby expose portions of a buried insulation layer of the SOI substrate. In this example, the method also includes performing an isotropic etching process to form recesses of any shape in the buried insulation layer, wherein the recesses extend laterally under a portion of the active layer, and forming an epi semiconductor material in at least the recesses in the buried insulation layer.
    Type: Application
    Filed: September 21, 2017
    Publication date: March 21, 2019
    Inventors: Shesh Mani Pandey, Jagar Singh, Judson R. Holt
  • Patent number: 10164099
    Abstract: One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shesh Mani Pandey, Pei Zhao, Baofu Zhu, Francis L. Benistant
  • Publication number: 20180337033
    Abstract: Devices and methods of fabricating devices are provided. One method includes: patterning an isolation gate disposed above a trench, the trench extending into a substrate; patterning a gate structure disposed above the substrate and adjacent the isolation gate; depositing a set of sidewall spacers on either side of the isolation gate and gate structure; etching a set of cavities between the isolation gate and gate structure and extending into the substrate; and epitaxially growing a set of epitaxial growths in the set of cavities, wherein the isolation gate is wider than the gate structure, and wherein epitaxial growths adjacent the isolation gate substantially conform to an oxide layer between the isolation gate and the trench, contacting at least a portion of a bottom surface and at least a portion of a side surface of the oxide layer.
    Type: Application
    Filed: May 16, 2017
    Publication date: November 22, 2018
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Shesh Mani PANDEY, Srikanth Balaji SAMAVEDAM, Jui-Hsuan FENG
  • Publication number: 20180286946
    Abstract: A shallow trench isolation (STI) structure is formed having a conventional STI trench structure formed of dielectric material extending into the substrate. A planarizing stack of nitride and oxide is formed above the STI trench structure (and optionally a dummy gate may be formed above this stack). After further conventional processing, the nitride layer results in a structure that extends laterally outward beyond the outer edges of the underlying STI structure—creating a shadow or umbrella structure. The S/D cavity is formed (between the active gate and dummy gate) and the epitaxial S/D regions are grown. The placement and configuration of the nitride layer assists in reducing the amount of substrate material removed adjacent the STI structure during the S/D region cavity formation.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 4, 2018
    Inventor: Shesh Mani Pandey
  • Patent number: 10083904
    Abstract: Methodologies and a device for reducing capacitance and improving profile control are provided. Embodiments include forming metal vias in a first dielectric layer; forming a graded interlayer dielectric over the metal vias; forming a metal layer in the graded ILD over one of the metal vias; and forming a hydrogenated amorphous silicon carbon film over the metal layer.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: September 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil Kumar Singh, Shesh Mani Pandey
  • Patent number: 10084093
    Abstract: During formation of a trench silicide contact, a sacrificial layer is incorporated into the trench directly over source/drain junctions prior to metallization of the trench. Selective removal of the sacrificial layer widens the trench proximate to the source/drain junctions, increasing the contact area and correspondingly decreasing the contact resistance between the source/drain junctions and a silicide layer.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: September 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shiv Kumar Mishra, Sunil Kumar Singh, Shesh Mani Pandey
  • Patent number: 10079308
    Abstract: The disclosure provides a vertical FinFET structure, including: a substrate including a first source/drain region; a looped channel region positioned on the first source/drain region of the substrate, the looped channel region having an inner perimeter which surrounds a hollow interior of the looped channel region; a first gate positioned within the hollow interior of the looped channel region, wherein the first gate is formed onto the looped channel region along the inner perimeter of the looped channel region; and a second source/drain region positioned on and overlying an upper surface of the looped channel region.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: September 18, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shesh Mani Pandey, Hui Zang, Josef S. Watts
  • Patent number: 10062689
    Abstract: A FinFET-type device is formed having a fin structure with vertically-oriented source/drain regions (with lightly doped extensions) and a channel region extending substantially perpendicular to the surface of the semiconductor substrate. A semiconductor stack is provided (or formed) having a first heavily doped layer and two lightly doped layer, with a channel region formed between the two lightly doped layers. The stack is etched to form fin structures (for the devices) and a gate stack is formed along the sidewalls of the channel region. A second heavily doped layer is selectively formed on the upper lightly doped layer. A portion of the first heavily doped layer and a portion of the lower lightly doped layer form a lower S/D region with a lightly doped extension region. Similarly, a portion of the second heavily doped layer and a portion of the upper lightly doped layer form an upper S/D region with a lightly doped extension region.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: August 28, 2018
    Assignee: Globalfoundries Inc.
    Inventor: Shesh Mani Pandey
  • Patent number: 10056486
    Abstract: Methods to reduce a width of a channel region of Si fins and the resulting devices are disclosed. Embodiments include forming a Si fin in a Si layer; forming a channel region over the Si fin including a dummy gate with a spacer on each side; forming S/D regions at opposite ends of the Si fin; removing the dummy gate, forming a cavity; thinning sidewalls of the Si fin; and forming a high-k/metal gate in the cavity.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shesh Mani Pandey, Pei Zhao, Zhenyu Hu
  • Publication number: 20180233415
    Abstract: A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.
    Type: Application
    Filed: April 6, 2018
    Publication date: August 16, 2018
    Inventors: Shesh Mani PANDEY, Baofu ZHU, Srikanth Balaji SAMAVEDAM
  • Publication number: 20180175198
    Abstract: One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.
    Type: Application
    Filed: February 6, 2018
    Publication date: June 21, 2018
    Inventors: Shesh Mani Pandey, Pei Zhao, Baofu Zhu, Francis L. Benistant
  • Patent number: 10002793
    Abstract: A gap fill method for sub-fin doping includes forming semiconductor fin arrays over a semiconductor substrate, forming a first dopant source layer over a first fin array and filling intra fin gaps within the first array, and forming a second dopant source layer over a second fin array and filling intra fin gaps within the second array. The first and second dopant source layers are recessed to expose a channel region of the fins. Thereafter, an annealing step is used to drive dopants from the dopant source layers locally into sub-fin regions of the fins below the channel regions.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 19, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, David P. Brunco, Jinping Liu, Baofu Zhu, Shesh Mani Pandey
  • Patent number: 10002797
    Abstract: Device structures and fabrication methods for a BiCMOS integrated circuit. A first fin and a second fin are formed on a semiconductor substrate. A gate electrode of a vertical field effect transistor is formed in association with the first fin. An emitter of a bipolar junction transistor is formed with an epitaxial growth process on the second fin, and a first source/drain region of the vertical field-effect transistor is concurrently formed with the epitaxial growth process on the first fin. The gate electrode and the first fin are arranged in a vertical direction between the source/drain region and the semiconductor substrate. The second fin is arranged in the vertical direction between the emitter and the semiconductor substrate.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: June 19, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Shesh Mani Pandey