Patents by Inventor Shesh Mani Pandey

Shesh Mani Pandey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210313321
    Abstract: One illustrative device disclosed herein includes at least one fin structure and an isolation structure comprising a stepped upper surface comprising a first region and a second region. The first region has a first upper surface and the second region has a second upper surface, wherein the first upper surface is positioned at a first level and the second upper surface is positioned at a second level and wherein the first level is below the second level. In this illustrative example, the device also includes a gate structure comprising a first portion and a second portion, wherein the first portion of the gate structure is positioned above the first upper surface of the isolation structure and above the at least one fin structure and wherein the second portion of the gate structure is positioned above the second upper surface of the isolation structure.
    Type: Application
    Filed: April 7, 2020
    Publication date: October 7, 2021
    Inventors: Haiting Wang, Sipeng Gu, Shesh Mani Pandey, Lixia Lei, Gregory Costrini
  • Patent number: 11094827
    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for multi-gate transistor devices having a short channel and a long channel component.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: August 17, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Yanping Shen, Xiaoxiao Zhang, Shesh Mani Pandey, Hui Zang
  • Patent number: 11049955
    Abstract: One illustrative device disclosed herein includes a transistor formed above a semiconductor-on-insulator (SOI) substrate, wherein the transistor comprises a gate structure, a sidewall spacer and source/drain regions, openings formed in the active layer in the source/drain regions adjacent the sidewall spacer, recesses formed in a buried insulation layer of the SOI substrate in the source/drain regions of the transistor, wherein the recesses extend laterally under a portion of the active layer, and an epi semiconductor material positioned in at least the recesses in the buried insulation layer.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: June 29, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Shesh Mani Pandey, Jagar Singh, Judson R. Holt
  • Publication number: 20210193526
    Abstract: Bipolar junction transistors include a collector, a base on the collector, and an emitter on the base. The base is between the collector and the emitter. The emitter comprises first portions and a second portion on the base. The first portions of the emitter are between the second portion of the emitter and the base. The first portions and the second portion comprise doped areas that are doped with the same polarity impurity in different concentrations. The base comprises a doped area that is doped with an opposite polarity impurity from the first and second portions of the emitter. The first portions of the emitter extend from the second portion of the emitter into the base. Specifically, the second portion has a bottom surface contacting the base, and the first portions comprise at least two separate impurity regions extending from the bottom surface of the second portion into the base.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Applicant: GLOBALFOUNDRIES U.S. Inc.
    Inventor: Shesh Mani Pandey
  • Publication number: 20210151451
    Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a selection gate electrode and a first gate insulation layer positioned above a substrate and a memory gate electrode positioned above the substrate and adjacent the selection gate electrode, wherein the memory gate electrode comprises a bottom surface and first and second opposing sidewall surfaces. This embodiment of the IC product also includes a plurality of layers of insulating material, wherein a first portion of the layers of insulating material is positioned between the first gate insulation layer and the first opposing sidewall of the memory gate electrode, a second portion of the layers of insulating material is positioned between the bottom surface of the memory gate electrode and the upper surface of the semiconductor substrate, and a third portion of the layers of insulating material is positioned on the second opposing sidewall of the conductive memory gate electrode.
    Type: Application
    Filed: November 14, 2019
    Publication date: May 20, 2021
    Inventors: Hui Zang, Ruilong Xie, Shesh Mani Pandey
  • Patent number: 10985244
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to n-well resistors and methods of manufacture. The structure includes: a substrate composed of a N-well implant region and a deep N-well implant region; and a plurality of shallow trench isolation regions extending into both the N-well implant region and a deep N-well implant region.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: April 20, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Shesh Mani Pandey, Chung Foong Tan, Baofu Zhu
  • Patent number: 10950692
    Abstract: One device disclosed herein includes, among other things, first and second active regions, a first source/drain contact positioned above the first active region, a second source/drain contact positioned above the second active region, and a dielectric material disposed between the first and second source/drain contacts, wherein the dielectric material defines an air gap cavity positioned between the first and second source/drain contacts.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Ruilong Xie, Vimal Kamineni, Shesh Mani Pandey, Hui Zang
  • Publication number: 20210050425
    Abstract: A semiconductor device comprises a gate stack structure having upper and lower sidewall portions and a bottom portion. The lower sidewall portions and the bottom portion having a high-k dielectric layer and a metal electrode layer that is positioned over the high-k dielectric layer. The upper sidewall portions having low-k dielectric layers over the lower sidewall portions. The low-k dielectric layers having side surfaces that are substantially coplanar with outer side surfaces of the high-k dielectric layer and are substantially coplanar with inner side surfaces of the metal electrode layer. A metal fill layer is over the metal electrode layer and the high-k dielectric layer in the lower sidewall portions and the bottom portion and between the low-k dielectric layers.
    Type: Application
    Filed: August 13, 2019
    Publication date: February 18, 2021
    Inventors: SHESH MANI PANDEY, JIEHUI SHU
  • Publication number: 20210043766
    Abstract: A laterally diffused metal-oxide semiconductor (LDMOS) device is disclosed. The LDMOS FET includes a gate structure between a source region and a drain region over a p-type semiconductor substrate; and a trench isolation partially under the gate structure and between the gate structure and the drain region. A p-well is under and adjacent the source region; and an n-well is under and adjacent the drain region. A counter doping region abuts and is between the p-well and the n-well, and is directly underneath the gate structure. The counter doping region increases drain-source breakdown voltage compares to conventional approaches.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Baofu Zhu, Shesh Mani Pandey, Jiehui Shu, Sipeng Gu, Haiting Wang
  • Publication number: 20200411638
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to n-well resistors and methods of manufacture. The structure includes: a substrate composed of a N-well implant region and a deep N-well implant region; and a plurality of shallow trench isolation regions extending into both the N-well implant region and a deep N-well implant region.
    Type: Application
    Filed: June 25, 2019
    Publication date: December 31, 2020
    Inventors: Shesh Mani PANDEY, Chung Foong TAN, Baofu ZHU
  • Publication number: 20200388707
    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for multi-gate transistor devices having a short channel and a long channel component.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 10, 2020
    Inventors: YANPING SHEN, XIAOXIAO ZHANG, SHESH MANI PANDEY, HUI ZANG
  • Patent number: 10840245
    Abstract: A semiconductor device comprising a substrate, a first fin and a second fin disposed on the substrate and an isolation material disposed on the substrate, wherein the isolation material separates the first fin and the second fin. A dielectric block is disposed between the first fin and the second fin, wherein the dielectric block is over the isolation material. A gate electrode covers the dielectric block.
    Type: Grant
    Filed: July 14, 2019
    Date of Patent: November 17, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shesh Mani Pandey, Jiehui Shu, Haiting Wang
  • Patent number: 10825910
    Abstract: Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Shesh Mani Pandey
  • Publication number: 20200335594
    Abstract: Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.
    Type: Application
    Filed: April 17, 2019
    Publication date: October 22, 2020
    Inventors: Hui Zang, Shesh Mani Pandey
  • Patent number: 10741451
    Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Shesh Mani Pandey, Chanro Park, Ruilong Xie
  • Patent number: 10727133
    Abstract: A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Qun Gao, Balaji Kannan, Shesh Mani Pandey, Haiting Wang
  • Patent number: 10699942
    Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chanro Park, Daniel Chanemougame, Steven Soss, Lars Liebmann, Hui Zang, Shesh Mani Pandey
  • Patent number: 10672710
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect structures with reduced capacitance and methods of manufacture. The method includes: forming one or more lower metal lines in a dielectric material; forming an airgap structure in an upper dielectric material above the one or more lower metal lines, by subjecting material to a curing process; and forming an upper metal structure above the airgap structure.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: June 2, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil Kumar Singh, Shesh Mani Pandey
  • Publication number: 20200135895
    Abstract: One illustrative device disclosed herein includes a transistor formed above a semiconductor-on-insulator (SOI) substrate, wherein the transistor comprises a gate structure, a sidewall spacer and source/drain regions, openings formed in the active layer in the source/drain regions adjacent the sidewall spacer, recesses formed in a buried insulation layer of the SOI substrate in the source/drain regions of the transistor, wherein the recesses extend laterally under a portion of the active layer, and an epi semiconductor material positioned in at least the recesses in the buried insulation layer.
    Type: Application
    Filed: December 26, 2019
    Publication date: April 30, 2020
    Inventors: Shesh Mani Pandey, Jagar Singh, Judson R. Holt
  • Publication number: 20200111713
    Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 9, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Shesh Mani Pandey, Chanro Park, Ruilong Xie