Patents by Inventor Shesh Mani Pandey

Shesh Mani Pandey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11894450
    Abstract: A disclosed structure includes a bipolar junction transistor (BJT) and a method of forming the structure. The structure includes a semiconductor layer on an insulator layer. The BJT includes a base region positioned laterally between emitter and collector regions. The emitter region includes an emitter portion of the semiconductor layer and an emitter semiconductor layer, which is within an emitter cavity in the insulator layer, which extends through an emitter opening in the emitter portion, and which covers the top of the emitter portion. The collector region includes a collector portion of the semiconductor layer and a collector semiconductor layer, which is within a collector cavity in the insulator layer, which extends through a collector opening in the collector portion, and which covers the top of the collector portion. Optionally, the structure also includes air pockets within the emitter and collector cavities.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: February 6, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Shesh Mani Pandey, Jeffrey B. Johnson
  • Publication number: 20240030341
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to laterally-diffused metal-oxide semiconductors and methods of manufacture. The structure includes: a drift region within a semiconductor substrate; a shallow trench isolation structure extending within the drift region; and a gate structure over the semiconductor substrate and extending within the shallow trench isolation structure.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Inventors: Shesh Mani PANDEY, Rajendran KRISHNASAMY
  • Patent number: 11881523
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a subcollector under a buried insulator layer; a collector above the subcollector; a base within the buried insulator layer; an emitter above the base; and contacts to the subcollector, the base and the emitter.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: January 23, 2024
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Shesh Mani Pandey, Vibhor Jain, Judson R. Holt
  • Patent number: 11869958
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a collector in a semiconductor substrate; a subcollector in the semiconductor substrate; an intrinsic base over the subcollector; an extrinsic base adjacent to the intrinsic base; an emitter over the intrinsic base; and an isolation structure between the extrinsic base and the emitter and which overlaps the subcollector.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: January 9, 2024
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Judson R. Holt, Shesh Mani Pandey, Vibhor Jain
  • Publication number: 20230420551
    Abstract: Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure comprises a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a first well and a second well in the semiconductor substrate beneath the dielectric layer. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the second well adjoins the first well along a p-n junction. The structure further comprises a first terminal and a second terminal above the dielectric layer, a first connection extending through the dielectric layer from the first terminal to the first well, and a second connection extending through the dielectric layer from the second terminal to the second well.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Shesh Mani Pandey, Souvick Mitra, Anindya Nath
  • Patent number: 11855197
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region comprising semiconductor-on-insulator material; a collector region confined within an insulator layer beneath the semiconductor-on-insulator material; an emitter region above the intrinsic base region; and an extrinsic base region above the intrinsic base region.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: December 26, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Shesh Mani Pandey, Alexander M. Derrickson, Judson R. Holt, Vibhor Jain
  • Patent number: 11848374
    Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a dielectric layer having a cavity, a first semiconductor layer on the dielectric layer, a collector including a portion on the first semiconductor layer, an emitter including a portion on the first semiconductor layer, and a second semiconductor layer that includes a first section in the cavity and a second section. The second section of the second semiconductor layer is laterally positioned between the portion of the collector and the portion of the emitter.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: December 19, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Shesh Mani Pandey, Jagar Singh, Judson Holt
  • Patent number: 11835764
    Abstract: Waveguide structures and methods of fabricating a waveguide structure. The structure includes a first waveguide core, a second waveguide core, and a third waveguide core adjacent to the first waveguide core and the second waveguide core. The third waveguide core is laterally separated from the first waveguide core by a first slot, and the third waveguide core is laterally separated from the second waveguide core by a second slot. The first waveguide core and the second waveguide core comprise a first material, and the third waveguide core comprises a second material that is different in composition from the first material.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: December 5, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Shesh Mani Pandey, Yusheng Bian, Judson Holt
  • Publication number: 20230369473
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a subcollector under a buried insulator layer; a collector above the subcollector; a base within the buried insulator layer; an emitter above the base; and contacts to the subcollector, the base and the emitter.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Inventors: Shesh Mani PANDEY, Vibhor JAIN, Judson R. HOLT
  • Publication number: 20230369474
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a collector in a semiconductor substrate; a subcollector in the semiconductor substrate; an intrinsic base over the subcollector; an extrinsic base adjacent to the intrinsic base; an emitter over the intrinsic base; and an isolation structure between the extrinsic base and the emitter and which overlaps the subcollector.
    Type: Application
    Filed: May 16, 2022
    Publication date: November 16, 2023
    Inventors: Judson R. HOLT, Shesh Mani PANDEY, Vibhor JAIN
  • Publication number: 20230352348
    Abstract: Disclosed are a semiconductor structure and method of forming the structure. The structure has a semiconductor layer. A gate structure is located on the semiconductor layer. The gate structure has a sidewall spacer having a first section on the semiconductor layer and positioned laterally adjacent to the gate structure and further having a second section above and wider than the first section and positioned laterally adjacent the gate structure. A source/drain region is on the semiconductor layer and positioned laterally adjacent to the first section and the second section of the sidewall spacer.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Applicant: GlobalFoundries U.S. Inc.
    Inventors: George R. Mulfinger, Md Nasir Uddin Bhuyian, Shesh Mani Pandey, Adam S. Rosenfeld, Selina A. Mala
  • Patent number: 11803009
    Abstract: Photonics structures including an optical component and methods of fabricating a photonics structure including an optical component. The photonics structure includes an optical component, a substrate having a cavity and a dielectric material in the cavity, and a dielectric layer positioned in a vertical direction between the optical component and the cavity. The optical component is positioned in a lateral direction to overlap with the cavity in the substrate.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: October 31, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Shesh Mani Pandey, Yusheng Bian, Steven M. Shank, Judson Holt
  • Patent number: 11749727
    Abstract: Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a first base layer, a second base layer, a first terminal positioned between the first base layer and the second base layer, a second terminal, and a third terminal. The first base layer, the second base layer, and the first terminal are positioned between the second terminal and the third terminal. For example, the first terminal may be positioned in a vertical direction between the first and second base layers.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: September 5, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Shesh Mani Pandey, Hong Yu, Alexander Derrickson
  • Publication number: 20230273369
    Abstract: Photonics structures including an optical component and methods of fabricating a photonics structure including an optical component. The photonics structure includes an optical component, a substrate having a cavity and a dielectric material in the cavity, and a dielectric layer positioned in a vertical direction between the optical component and the cavity. The optical component is positioned in a lateral direction to overlap with the cavity in the substrate.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 31, 2023
    Inventors: Shesh Mani Pandey, Yusheng Bian, Steven M. Shank, Judson Holt
  • Publication number: 20230266526
    Abstract: Disclosed is an optical waveguide including a waveguide core and waveguide cladding surrounding the waveguide core. The waveguide cladding includes at least one stack of cladding material layers positioned laterally adjacent to a sidewall of the waveguide core such that each cladding material layer in the stack abuts the sidewall of the waveguide core. Each of the cladding material layers in the stack has a smaller refractive index than the waveguide core and at least two of the cladding material layers in the stack have different refractive indices, thereby tailoring field confinement and reshaping the optical mode. Different embodiments include different numbers of cladding material layers in the stack, different stacking orders of the cladding material layers, different waveguide core types, symmetric or asymmetric cladding structures on opposite sides of the waveguide core, etc. Also disclosed is a method of forming the optical waveguide.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Applicant: GlobalFoundries U.S. Inc.
    Inventors: Shesh Mani Pandey, Yusheng Bian, Francis O. Afzal
  • Publication number: 20230244033
    Abstract: Waveguide structures and methods of fabricating a waveguide structure. The structure includes a first waveguide core, a second waveguide core, and a third waveguide core adjacent to the first waveguide core and the second waveguide core. The third waveguide core is laterally separated from the first waveguide core by a first slot, and the third waveguide core is laterally separated from the second waveguide core by a second slot. The first waveguide core and the second waveguide core comprise a first material, and the third waveguide core comprises a second material that is different in composition from the first material.
    Type: Application
    Filed: January 31, 2022
    Publication date: August 3, 2023
    Inventors: Shesh Mani Pandey, Yusheng Bian, Judson Holt
  • Publication number: 20230231041
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region comprising semiconductor-on-insulator material; a collector region confined within an insulator layer beneath the semiconductor-on-insulator material; an emitter region above the intrinsic base region; and an extrinsic base region above the intrinsic base region.
    Type: Application
    Filed: January 20, 2022
    Publication date: July 20, 2023
    Inventors: Shesh Mani PANDEY, Alexander M. DERRICKSON, Judson R. HOLT, Vibhor JAIN
  • Publication number: 20230178637
    Abstract: The disclosure provides a bipolar transistor structure with multiple bases, and related methods. A bipolar transistor structure includes a first emitter/collector (E/C) material above an insulator. The first E/C material has first sidewall and a second sidewall over the insulator. A first base is above the insulator adjacent the first sidewall of the first E/C material. A second base is above the insulator adjacent the second sidewall of the first E/C material. A second E/C material is above the insulator and adjacent the first base. A width of the first base between the first E/C material and the second E/C material is less than a width of the first E/C material, and the first base protrudes horizontally outward from an end of the first E/C material and an end of the second E/C material.
    Type: Application
    Filed: April 15, 2022
    Publication date: June 8, 2023
    Inventor: Shesh Mani Pandey
  • Publication number: 20230155011
    Abstract: A disclosed structure includes a bipolar junction transistor (BJT) and a method of forming the structure. The structure includes a semiconductor layer on an insulator layer. The BJT includes a base region positioned laterally between emitter and collector regions. The emitter region includes an emitter portion of the semiconductor layer and an emitter semiconductor layer, which is within an emitter cavity in the insulator layer, which extends through an emitter opening in the emitter portion, and which covers the top of the emitter portion. The collector region includes a collector portion of the semiconductor layer and a collector semiconductor layer, which is within a collector cavity in the insulator layer, which extends through a collector opening in the collector portion, and which covers the top of the collector portion. Optionally, the structure also includes air pockets within the emitter and collector cavities.
    Type: Application
    Filed: March 16, 2022
    Publication date: May 18, 2023
    Applicant: GlobalFoundries U.S. Inc.
    Inventors: Shesh Mani Pandey, Jeffrey B. Johnson
  • Publication number: 20230137751
    Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure comprises a first terminal including a first raised semiconductor layer, a second terminal including a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The structure further comprises a modulator including a semiconductor layer in direct contact with the base layer. The base layer has a first conductivity type, and the semiconductor layer has a second conductivity type opposite to the first conductivity type.
    Type: Application
    Filed: July 25, 2022
    Publication date: May 4, 2023
    Inventor: Shesh Mani Pandey