Abstract: An integrated circuit 2 includes one or more transaction masters 8, 10, 12, 4 for issuing data transactions via interconnect circuitry 20. Debug access port circuitry is configured to respond to debug commands received from a debug controller 6 to generate barrier transactions which are issued to the interconnect circuitry. The interconnect circuitry responds to the received barrier transactions by constraining a relative ordering of at least some of the data transactions as they pass through the interconnect circuitry.

Abstract: A count value generator includes an input for receiving a synchronizing count value, a counter configured to increment at a local frequency, the local frequency being faster than the synchronizing frequency, and an interpolator for determining a frequency ratio between the local frequency and the synchronizing frequency and for determining an increment value for the counter dependent on a relative amount of a maximum value of the counter with respect to the frequency ratio is disclosed. The counter generates a count value including a predetermined number of bits representing integer values and output as the lower order bits of the output count value and additional lower order bits that represent fractional portions of the integer values. The counter includes output circuitry for outputting the synchronizing count value and the predetermined number of bits representing integer values generated by the counter as the lower order bits of the count value.

Abstract: A count value generator includes an input for receiving a synchronising count value, a counter configured to increment at a local frequency, the local frequency being faster than the synchronising frequency, and an interpolator for determining a frequency ratio between the local frequency and the synchronising frequency and for determining an increment value for the counter dependent on a relative amount of a maximum value of the counter with respect to the frequency ratio is disclosed. The counter generates a count value including a predetermined number of bits representing integer values and output as the lower order bits of the output count value and additional lower order bits that represent fractional portions of the integer values. The counter includes output circuitry for outputting the synchronising count value and the predetermined number of bits representing integer values generated by the counter as the lower order bits of the count value.

Abstract: An integrated circuit 2 includes one or more transaction masters 8, 10, 12, 4 for issuing data transactions via interconnect circuitry 20. Debug access port circuitry is configured to respond to debug commands received from a debug controller 6 to generate barrier transactions which are issued to the interconnect circuitry. The interconnect circuitry responds to the received barrier transactions by constraining a relative ordering of at least some of the data transactions as they pass through the interconnect circuitry.