Abstract: A selectively upgradeable disaggregated server is generally described herein. An example modular server unit, the modular server unit includes a processor module coupled to an input/output (I/O) module via a connector. The processor module to communicate with the I/O module via the connector to store and retrieve data. The processor module is a separate hardware unit from the I/O module.

Abstract: Examples are disclosed for receiving or gathering asset information associated with computing devices housed in respective decentralized locations. The gathered or received asset information may be stored. A portion of the computing devices may be grouped based on the stored asset information to create a virtual rack. An operating parameter of at least some of the computing devices included in the virtual rack may then be managed or controlled.

Abstract: A selectively upgradeable disaggregated server is generally described herein. An example modular server unit, the modular server unit includes a processor module coupled to an input/output (I/O) module via a connector. The processor module to communicate with the I/O module via the connector to store and retrieve data. The processor module is a separate hardware unit from the I/O module.

Abstract: Examples are disclosed for operating, managing or controlling one or more network computing devices housed in a chassis capable of being mounting in a ceiling space or a floor space for a room. Operating, managing or controlling may include adjusting one or more fans to direct airflow either away or towards the room or powering a light emitting diode array attached with the chassis to provide lighting to the room. Examples are also disclosed for using an aggregator to operate, manage or control an array of network computing devices separately housed in chassis capable of being mounted in a ceiling space or floor space for one or more rooms.

Abstract: Examples are disclosed for managing power and performance of multi-socket processors. In some examples, a utilization rate of a first processor circuitry in a first processor socket may be determined. An active memory ratio of a cache for the first processor circuitry may be compared to a threshold ratio or a data traffic rate between the first processor circuitry and a second processor circuitry in a second processor socket may be compared to a threshold rate. According to some examples, a first power state of the first processor circuitry may be changed based on the determined utilization rate. The first power state may also be changed based on the comparison of the active memory ratio to the threshold ratio or the comparison of the data traffic rate to the threshold rate.

Abstract: Examples are disclosed for managing power and performance of multi-socket processors. In some examples, a utilization rate of a first processor circuitry in a first processor socket may be determined. An active memory ratio of a cache for the first processor circuitry may be compared to a threshold ratio or a data traffic rate between the first processor circuitry and a second processor circuitry in a second processor socket may be compared to a threshold rate. According to some examples, a first power state of the first processor circuitry may be changed based on the determined utilization rate. The first power state may also be changed based on the comparison of the active memory ratio to the threshold ratio or the comparison of the data traffic rate to the threshold rate.

Abstract: Examples are disclosed for managing power and performance of multi-socket processors. In some examples, a utilization rate of a first processor circuitry in a first processor socket may be determined. An active memory ratio of a cache for the first processor circuitry may be compared to a threshold ratio or a data traffic rate between the first processor circuitry and a second processor circuitry in a second processor socket may be compared to a threshold rate. According to some examples, a first power state of the first processor circuitry may be changed based on the determined utilization rate. The first power state may also be changed based on the comparison of the active memory ratio to the threshold ratio or the comparison of the data traffic rate to the threshold rate.

Abstract: Examples are disclosed for managing power and performance of multi-socket processors. In some examples, a utilization rate of a first processor circuitry in a first processor socket may be determined. An active memory ratio of a cache for the first processor circuitry may be compared to a threshold ratio or a data traffic rate between the first processor circuitry and a second processor circuitry in a second processor socket may be compared to a threshold rate. According to some examples, a first power state of the first processor circuitry may be changed based on the determined utilization rate. The first power state may also be changed based on the comparison of the active memory ratio to the threshold ratio or the comparison of the data traffic rate to the threshold rate.

Abstract: Examples are disclosed for receiving or gathering asset information associated with computing devices housed in respective decentralized locations. The gathered or received asset information may be stored. A portion of the computing devices may be grouped based on the stored asset information to create a virtual rack. An operating parameter of at least some of the computing devices included in the virtual rack may then be managed or controlled.

Abstract: Examples are disclosed for operating, managing or controlling one or more network computing devices housed in a chassis capable of being mounting in a ceiling space or a floor space for a room. Operating, managing or controlling may include adjusting one or more fans to direct airflow either away or towards the room or powering a light emitting diode array attached with the chassis to provide lighting to the room. Examples are also disclosed for using an aggregator to operate, manage or control an array of network computing devices separately housed in chassis capable of being mounted in a ceiling space or floor space for one or more rooms.

Abstract: An embodiment may include at least one first process to be executed, at least in part, by circuitry. The at least one first process may select, at least in part, from a plurality of processor cores, one or more processor cores to execute, at least in part, at least one second process. The at least one first process may select, at least in part, the one or more processor cores based at least in part upon whether at least one inter-dependency exists, at least in part, between the at least one second process and at least one third process also to be executed by the one or more processor cores. Many alternatives, variations, and modifications are possible.

Abstract: An embodiment may include at least one first process to be executed, at least in part, by circuitry. The at least one first process may select, at least in part, from a plurality of processor cores, one or more processor cores to execute, at least in part, at least one second process. The at least one first process may select, at least in part, the one or more processor cores based at least in part upon whether at least one inter-dependency exists, at least in part, between the at least one second process and at least one third process also to be executed by the one or more processor cores. Many alternatives, variations, and modifications are possible.