Abstract: A computer-implemented method, system and computer program product for recommending design changes in designing a digital integrated circuit. An analysis of the digital integrated circuit being designed is performed, where the result of such an analysis involves violations being identified and stored. A stored violation, such as a cross-domain, cross-hierarchy and multi-cycle violation, may then be analyzed to identify a root cause of the violation using a rule. Such a rule may be used for triaging various failures in the cross-domain, cross-hierarchy and/or multi-cycle violation of the digital integrated circuit. A design change in the design of the digital integrated circuit may then be recommended based on the identified root cause of the violation. In this manner, the root cause of failures are effectively identified in the design of digital integrated circuits using an offline analysis of cross-domain, cross-hierarchy and/or multi-cycle violations using a rules-based approach.

Abstract: An electronic design automation (EDA) data processing system includes a version graph database and a controller. The version graph database stores a plurality of different versions of graph data sets. Each graph data set corresponds to a respective circuit component located at a given hierarchical level of a semiconductor chip design and each graph data set tagged with a version identifier (ID) indicating the version thereof. The controller determines a hierarchical circuit included in the semiconductor chip and determines a plurality of targeted circuit components that define the hierarchical circuit. The controller determines targeted graph data sets from the versions graph database that correspond to the targeted circuit components, and obtains the targeted graph data sets having matching version IDs such that the targeted graph data sets are the same version.

Abstract: A system and method to perform an ordered write of timing analysis data obtained in parallel during integrated circuit development process two or more data sets with two or more processors in parallel. The two or more data sets result from timing analysis and correspond with two or more paths, each path includes a set of interconnected components, and the processing includes collecting and formatting information to obtain the timing analysis data associated with each of the two or more paths. The method includes determining a next timing analysis data using an ordered list of the two or more data sets that correspond with the timing analysis data, consulting an availability vector to determine whether the next timing analysis data is available, and writing the next timing analysis data as soon as it is available prior to completion of the processing of others of the two or more data sets.

Abstract: A system and method to perform an ordered write of timing analysis data obtained in parallel during integrated circuit development process two or more data sets with two or more processors in parallel. The two or more data sets result from timing analysis and correspond with two or more paths, each path includes a set of interconnected components, and the processing includes collecting and formatting information to obtain the timing analysis data associated with each of the two or more paths. The method includes determining a next timing analysis data using an ordered list of the two or more data sets that correspond with the timing analysis data, consulting an availability vector to determine whether the next timing analysis data is available, and writing the next timing analysis data as soon as it is available prior to completion of the processing of others of the two or more data sets.

Abstract: A statistical timing analysis using statistical timing macro-models considering statistical timing value entries such as input slew and output load is disclosed. That statistical timing analysis calculates a statistical timing quantity based on statistical timing value entries based on a statistical timing (ST) macro-model of a selected macro of an integrated circuit (IC) design that includes statistical timing quantities as a function of deterministic timing value entries.

Abstract: A method of performing variation aware timing analysis for an integrated circuit, a system, and a computer program product are described. The method includes determining one or more voltage waveforms at an output of a first component of the integrated circuit based on respective one or more first processing conditions, and storing waveform information based on the one or more voltage waveforms. The method also includes obtaining an input voltage waveform at an input of a second component of the integrated circuit for a second processing condition based on processing the waveform information, the output of the first component being the input of the second component, and performing the variation aware timing analysis for the second component based on the input voltage waveform.

Abstract: A method of performing variation aware timing analysis for an integrated circuit, a system, and a computer program product are described. The method includes determining one or more voltage waveforms at an output of a first component of the integrated circuit based on respective one or more first processing conditions, and storing waveform information based on the one or more voltage waveforms. The method also includes obtaining an input voltage waveform at an input of a second component of the integrated circuit for a second processing condition based on processing the waveform information, the output of the first component being the input of the second component, and performing the variation aware timing analysis for the second component based on the input voltage waveform.

Abstract: A statistical timing analysis using statistical timing macro-models considering statistical timing value entries such as input slew and output load is disclosed. That statistical timing analysis calculates a statistical timing quantity based on statistical timing value entries based on a statistical timing (ST) macro-model of a selected macro of an integrated circuit (IC) design that includes statistical timing quantities as a function of deterministic timing value entries.