Patents by Inventor Sheung-Fan Wen

Sheung-Fan Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD OF OPERATING A MEMORY DEVICE HAVING DECOUPLED ADDRESS AND DATA ACCESS
    Publication number: 20020199055
    Abstract: A buffer manager provides address information for reading and writing data to an SDRAM. The address information is translated from a flat memory address space into an SDRAM address space. The buffer manager operates based upon a first clock and the SDRAM operates based upon a second clock. Accordingly, a synchronization circuit synchronizes the data. The translation of address information occurs simultaneously with the synchronization of data.
    Type: Application
    Filed: June 6, 2002
    Publication date: December 26, 2002
    Inventor: Sheung-Fan Wen
  • Method of operating a memory device having decoupled address and data access
    Patent number: 6484248
    Abstract: A buffer manager provides address information for reading and writing data to an SDRAM. The address information is translated from a flat memory address space into an SDRAM address space. The buffer manager operates based upon a first clock and the SDRAM operates based upon a second clock. Accordingly, a synchronization circuit synchronizes the data. The translation of address information occurs simultaneously with the synchronization of data.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: November 19, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Sheung-Fan Wen
  • Decoupled address and data access to an SDRAM
    Patent number: 6418518
    Abstract: A buffer manager provides address information for reading and writing data to an SDRAM. The address information is translated from a flat memory address space into an SDRAM address space. The buffer manager operates based upon a first clock and the SDRAM operates based upon a second clock. Accordingly, a synchronization circuit synchronizes the data. The translation of address information occurs simultaneously with the synchronization of data.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: July 9, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Sheung-Fan Wen
  • Dual port memory control signals with synchronized read and write pointers
    Patent number: 6259650
    Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: July 10, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Sheung-Fan Wen
  • Dual port memory operation method with synchronized read and write pointers
    Patent number: 6212122
    Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: April 3, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Sheung-Fan Wen
  • SDRAM address translator
    Patent number: 6205511
    Abstract: A buffer manager divides a memory space into a plurality of buffers. Each buffer occupies a plurality of sequential memory locations. The sequential memory locations include a start and an end address. To write data to a buffer, the buffer manager provides a start address and burst size to an address translator. The address translator converts the start address and the burst size to SDRAM memory address locations. The start and end address of each buffer is mapped to a different bank in the SDRAM memory.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: March 20, 2001
    Assignee: National Semiconductor Corp.
    Inventor: Sheung-Fan Wen
  • Dual port memory with synchronized read and write pointers
    Patent number: 6166963
    Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: December 26, 2000
    Assignee: National Semiconductor Corporation
    Inventor: Sheung-Fan Wen
  • Synchronized circuit for coordinating address pointers across clock domains
    Patent number: 6134155
    Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: October 17, 2000
    Assignee: National Semiconductor Corporation
    Inventor: Sheung-Fan Wen