Abstract: A high resolution quadrilinear CCD imager array which incorporates a unique on-chip multiplexing technique. The multiplexing is accomplished in two consecutive steps. First the two video outputs on either side of the sensor array are multiplexed through a CCD channel. This multiplexed output is then sensed through a source follower circuit, one on either side of said sensor array. A non-overlapping clocking technique is used to sample and hold the signals on either side and simultaneously the second level of multiplexing is also accomplished, giving a 4:1 video multiplexed output. The final signal is sensed through a second stage source follower circuit. Bad pixel deletion is effected by overriding the sample and hold signal.