Abstract: Methods, systems, and devices for memory cell capacitor structures for three-dimensional memory arrays are described. A memory device may include a memory array including multiple levels of memory cells that are each separated from another level by a respective dielectric layer. A memory cell at a first level of the memory array may include a channel portion and a capacitor operable to store a logic state of the memory cell. A first portion of the capacitor may be located between the channel portion and a voltage source coupled with the memory cell. A second portion of the capacitor may be in a cavity in a dielectric layer between the first level and a second level of the memory array. The second portion of the capacitor may be located between the channel portion and a word line coupled with a channel portion of a second memory cell at the second level.

Abstract: A method performed by a memory device to perform all levels programming with loop dependent pillar boosting is provided. The method comprises, in at least one loop of a plurality of operational loops performed by a memory controller, causing a first bias voltage to be applied to a plurality of word lines and a target bit line. The method further comprises causing a set of ramping voltages to be applied to the plurality of word lines over a plurality of ramp-up periods. Each ramping voltage of the set of ramping voltages is incremented by a delta voltage in a corresponding ramp-up period of the plurality of ramp-up period. The method further comprises identifying a target ramp-up period for the target memory cell. The method further comprises, during the identified target ramp-up period, causing a second bias voltage to be applied to the target bit line.

Abstract: Systems and methods for two-stage memory cell programming. An example memory device comprises: a memory array; and a controller coupled to the memory array, the controller to perform operations comprising: receiving a request to perform a memory programming operation with respect to a target set of memory cells electrically coupled to a target wordline and a set of target bitlines; performing a first stage of the memory programming operation by causing a ramping up programming voltage to be applied to the target wordline while causing one or more pillars associated with the target memory cells to be boosted in a staggered manner; and performing a second stage of the memory programming operation by causing a programming voltage to be applied to the target wordline, while selectively applying bias voltage to the set of target bitlines.

Abstract: Memories might include a controller configured to cause the memory to develop a respective voltage level in a channel of each memory cell of a plurality of memory cells selected for a programming operation, apply a programming voltage level to a selected access line of the programming operation, determine a number of memory cells of the plurality of memory cells passing verify for each data state of a subset of data states, selectively modify values of the respective channel voltage levels in response to at least the determined number of memory cells passing verify for each of the data states of the subset of data states, and perform a subsequent programming operation using the selectively modified values of the channel voltage levels.

Abstract: Memories might include an array of memory cells having a plurality of strings of series-connected memory cells each formed around a respective channel material structure, and a controller configured to determine a data state stored to a selected string of series-connected memory cells in response to charge stored to its respective channel material structure.

Abstract: Control logic in a memory device causes a programming pulse of a programming operation to be applied to a selected wordline associated with a plurality of memory cells of a memory device to be programmed to a target voltage level representing a programming level, where a charge loss associated with the plurality of memory cells occurs following application of the programming pulse. The selected wordline is discharged to establish an erase voltage level on the plurality of memory cells and accelerate the charge loss associated with the plurality of memory cells. The control logic performs a program verify operation corresponding to the programming level associated with the plurality of memory cells.

Abstract: Control logic in a memory device initiates a program operation including application of a set of programming pulses to a wordline associated with one or more memory cells of a memory array to be programmed to a set of programming levels. During a first sub-phase of the programming operation, the control logic causes each programming pulse to program a first subset of programming levels, wherein programming of a second subset of one or more programming levels is inhibited. During a second sub-phase of the programming operation, the control logic programs the second subset of one or more programming levels, where the second subset of one or more of the plurality of programming levels are associated with one or more lower voltage levels than the first subset of the plurality of programming levels.

Abstract: Memories might include a controller configured to cause the memory to develop a respective voltage level in a channel of each memory cell of a plurality of subsets of memory cells selected for a programming operation, wherein each of the memory cells is connected to a selected access line of the programming operation, and wherein each of the subsets of memory cells corresponds to a respective voltage level of the plurality of voltage levels in a one-to-one relationship; and to apply a programming voltage level of the programming operation to the selected access line. Each of the memory cells has a respective desired data state of a plurality of possible data states of the programming operation, and the respective desired data states of the memory cells of at least one of the subsets of memory cells includes two or more data states of the plurality of possible data states.

Abstract: A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, and wordlines coupled with first and second pillars. Control logic may cause wordlines to be discharged after a program pulse is applied to selected wordline. The control logic may apply a supply voltage to second data line to cause a voltage of second pillar to float. The control logic may apply a ground voltage to the first data line to inhibit soft erase associated with the selected wordline via first pillar.

Abstract: Memories might include an array of memory cells having a plurality of strings of series-connected memory cells and a controller configured to cause to memory to access a first string of series-connected memory cells of the plurality of strings of series-connected memory cells in a first mode of operation for volatile storage of data to the first string of series-connected memory cells, and access a second string of series-connected memory cells of the plurality of strings of series-connected memory cells in a second mode of operation for non-volatile storage of respective data to each memory cell of a plurality of memory cells of the second string of series-connected memory cells

Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a selected wordline associated with a set of memory cells to be programmed to a target voltage level representing a programming level. Voltage levels of the selected wordline and one or more unselected wordlines of the memory array are discharged to approximately a ground voltage level and a bitline voltage level is applied to a bitline corresponding to the programming level. The selected wordline and a set of unselected wordlines are charged to approximately a pass voltage level followed by the discharge of the selected wordline to a reverse bias level to establish an erase voltage level on the set of memory cells. The control logic further performs a program verify operation corresponding to the programming level associated with the set of memory cells.

Abstract: Control logic in a memory device initiates a program operation including application of a set of programming pulses to a wordline associated with one or more memory cells of a memory array to be programmed to a set of programming levels, where each programming level of the set of programming levels is programmed by each programming pulse. The control logic determines that a program voltage of a programming pulse of the set of programming pulses reaches a maximum program voltage level. In response to the determining, applying a subsequent programming pulse having a subsequent program voltage that is below the maximum program voltage level.

Abstract: Control logic in a memory device initiates a program operation including application of a set of programming pulses to a wordline associated with one or more memory cells of a memory array to be programmed to a set of programming levels, where each programming level of the set of programming levels is programmed by each programming pulse. The control logic determines that a program voltage of a programming pulse of the set of programming pulses reaches a maximum program voltage level. In response to the determining, during a subsequent programming pulse following the programming pulse, adjusting a first voltage associated with boosting a pillar voltage, a second voltage applied to a bitline, and a third voltage applied to the wordline to establish a subsequent program voltage of the subsequent programming pulse that is below the maximum program voltage level.

Abstract: Control logic causes, during a program operation, a programming pulse to be applied to a memory cell of a set of memory cells to be programmed to a first programming level of a set of programming levels. The control logic further determines that a condition associated with the memory cell is satisfied. The control logic further executes a level shifting operation in response to the condition to be satisfied.

Abstract: An example memory device includes: a memory array; and a controller coupled to the memory array, the controller to perform the following operations: identifying a set of memory cells for performing a memory programming operation, such that the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, such that the first voltage is incremented every time period over a sequence of time periods; causing a second voltage to be applied to a first bitline, such that the second voltage is incremented during a first time period of the sequence of time periods; and causing a third voltage to be applied to a second bitline, such that the third voltage is incremented during a second time period of the sequence of time periods.

Abstract: Memories might include a plurality of strings of series-connected memory cells, each corresponding to a respective digit of a plurality of digits of a multiplicand, and might further include a controller configured to cause the memory to generate respective current flows through the plurality of strings of series-connected memory cells for each digit of a plurality of digits of a multiplier having respective current levels indicative of values of each digit of the plurality of digits of the multiplier times the multiplicand, to convert the respective current levels to respective digital values indicative of the values and magnitudes of each digit of the plurality of digits of the multiplier times the multiplicand, and to sum the respective digital value of each digit of the plurality of digits of the multiplier.

Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes, at a first time during a program operation, a first programming pulse to be applied to a memory cell of the memory array to be programmed to a first programming level. The control logic further performs a program verify operation corresponding to the first programming level and compares a threshold voltage of the memory cell to one or more program verify voltage levels of the program verify operation to determine whether a condition is satisfied. The control logic further executes a level shifting operation in response to the condition to be satisfied.

Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. At a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. At a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. In view of the second data, a level shifting operation associated with the memory cell is caused to be executed.

Abstract: Described are systems and methods for all level coarse/fine programming of memory cells.

Abstract: Described are systems and methods for concurrent slow-fast memory cell programming.