Abstract: An example memory device includes: a memory array; and a controller coupled to the memory array, the controller to perform the following operations: identifying a set of memory cells for performing a memory programming operation, such that the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, such that the first voltage is incremented every time period over a sequence of time periods; causing a second voltage to be applied to a first bitline, such that the second voltage is incremented during a first time period of the sequence of time periods; and causing a third voltage to be applied to a second bitline, such that the third voltage is incremented during a second time period of the sequence of time periods.

Abstract: Memories might include a plurality of strings of series-connected memory cells, each corresponding to a respective digit of a plurality of digits of a multiplicand, and might further include a controller configured to cause the memory to generate respective current flows through the plurality of strings of series-connected memory cells for each digit of a plurality of digits of a multiplier having respective current levels indicative of values of each digit of the plurality of digits of the multiplier times the multiplicand, to convert the respective current levels to respective digital values indicative of the values and magnitudes of each digit of the plurality of digits of the multiplier times the multiplicand, and to sum the respective digital value of each digit of the plurality of digits of the multiplier.

Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes, at a first time during a program operation, a first programming pulse to be applied to a memory cell of the memory array to be programmed to a first programming level. The control logic further performs a program verify operation corresponding to the first programming level and compares a threshold voltage of the memory cell to one or more program verify voltage levels of the program verify operation to determine whether a condition is satisfied. The control logic further executes a level shifting operation in response to the condition to be satisfied.

Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. At a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. At a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. In view of the second data, a level shifting operation associated with the memory cell is caused to be executed.

Abstract: Described are systems and methods for all level coarse/fine programming of memory cells.

Abstract: Described are systems and methods for concurrent slow-fast memory cell programming.

Abstract: Control logic in a memory device causes a first set of pulses corresponding to a first voltage ramp slope level to be applied to a memory cell during a first time interval of an execution of a memory access operation. In response to determining a transition time has been reached, the control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first voltage ramp slope level and the second voltage ramp slope level are different.

Abstract: Control logic in a memory device initiates a program operation including a first phase including applying a ramping voltage level to a set of wordlines of a memory device to boost a set of pillar voltages and a second phase including applying a set of programming pulses to a wordline associated with one or more memory cells of the memory device to be programmed to a set of programming levels, wherein each programming level of the set of programming levels is programmed by each programming pulse. During the first phase of the program operation, a first voltage applied to a drain-side select line (SGD) is adjusted from a first SGD voltage level to a second SGD voltage level.

Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.

Abstract: Control logic in a memory device, identifies a set of a plurality of memory cells associated with a selected wordline to be programmed to respective programming levels during a program operation and causes a set of a plurality of pillars with which the set of the plurality of memory cells are associated to be boosted to respective pillar voltages corresponding to the respective programming levels.

Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. At a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. At a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. In view of the second data, a level shifting operation associated with the memory cell is caused to be executed.

Abstract: A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, and wordlines coupled with first and second pillars. Control logic may cause wordlines to be discharged after a program pulse is applied to selected wordline. The control logic may apply a supply voltage to second data line to cause a voltage of second pillar to float. The control logic may apply a ground voltage to the first data line to inhibit soft erase associated with the selected wordline via first pillar.

Abstract: Control logic in a memory device causes a first programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a wordline associated with a memory cell to be programmed to a first target voltage level representing a first programming level. The control logic further performs a program verify operation corresponding to the first programming level to determine that a threshold voltage of the memory cell exceeds the first target voltage level. The control logic further causes first data to be stored in a cache, the first data indicating that the threshold voltage of the memory cell exceeds the first target voltage level. The cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the first target voltage level. In view of the second data, a further programming pulse is caused to be applied to the wordline associated with the memory cell at a reduced programming stress level.

Abstract: Memories might include an array of memory cells having a plurality of strings of series-connected memory cells and a controller configured to cause to memory to access a first string of series-connected memory cells of the plurality of strings of series-connected memory cells in a first mode of operation for volatile storage of data to the first string of series-connected memory cells, and access a second string of series-connected memory cells of the plurality of strings of series-connected memory cells in a second mode of operation for non-volatile storage of respective data to each memory cell of a plurality of memory cells of the second string of series-connected memory cells

Abstract: A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, wordlines coupled with first and second pillars. Control logic is to cause: wordlines to be discharged after a program pulse is applied to selected wordline; a supply voltage be applied to second data line to cause a voltage of second pillar to float; a ground voltage be applied to first data line to inhibit soft erase via first pillar; unselected wordlines be charged to boost channel voltages in memory cells coupled with the second pillar; and one of the ground voltage or a negative voltage be applied to the selected wordline to increase soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline, causing a threshold voltage stored in the memory cell to be erased.

Abstract: Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.

Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and applies, during a first time period of the program operation, a ramping wordline voltage to a set of wordlines associated with the memory array. The control logic causes, during the first time period, a disconnection of a set of pillars associated with the set of memory cells from a voltage supply and ground voltage, wherein each pillar corresponds to a programming level of a set of programming levels. The control logic further causes, during a second time period of the program operation, a set of programming pulses to be applied to the set of memory cells, wherein each programming pulse of the set of programming pulses programs each programming level of the set of programming levels associated with the identified set of memory cells.

Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.

Abstract: Control logic in a memory device initiates a program operation including application of a set of programming pulses to a wordline associated with one or more memory cells of a memory array to be programmed to a set of programming levels, where each programming level of the set of programming levels is programmed by each programming pulse. The control logic determines that a program voltage of a programming pulse of the set of programming pulses reaches a maximum program voltage level. In response to the determining, during a subsequent programming pulse following the programming pulse, adjusting a first voltage associated with boosting a pillar voltage, a second voltage applied to a bitline, and a third voltage applied to the wordline to establish a subsequent program voltage of the subsequent programming pulse that is below the maximum program voltage level.

Abstract: Methods, systems, and devices for memory cell capacitor structures for three-dimensional memory arrays are described. A memory device may include a memory array including multiple levels of memory cells that are each separated from another level by a respective dielectric layer. A memory cell at a first level of the memory array may include a channel portion and a capacitor operable to store a logic state of the memory cell. A first portion of the capacitor may be located between the channel portion and a voltage source coupled with the memory cell. A second portion of the capacitor may be in a cavity in a dielectric layer between the first level and a second level of the memory array. The second portion of the capacitor may be located between the channel portion and a word line coupled with a channel portion of a second memory cell at the second level.