Patents by Inventor Shi Chen

Shi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12199139
    Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Chen Hsu, Hsin-Li Cheng, Jyun-Ying Lin, Yingkit Felix Tsui, Shu-Hui Su, Shi-Min Wu
  • Publication number: 20250013354
    Abstract: The present disclosure provides an information processing method and apparatus, an electronic device, and a storage medium. The present disclosure provides an information processing method. The method includes: receiving a first document, so as to perform preset processing on the first document; determining, based on document content of the first document, or the document content and associated information of the first document, whether there is an alert item in the first document that satisfies a preset condition; and displaying the first document in association with the alert item in response to there being the alert item in the first document, where the alert item is displayed in association with category information.
    Type: Application
    Filed: November 14, 2022
    Publication date: January 9, 2025
    Inventors: Zikai QI, Shi CHEN, Xiao XU, Ying XU, Yifan DING, Dapeng CAO, Yu DENG, Kuo PEI, Yangyang XIANG, Jieke LIN
  • Publication number: 20250006721
    Abstract: Techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. In an example, an integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. Additionally, the various rows of cells may contain semiconductor nanoribbons having different widths between different rows. For example, any number of first rows of cells can each have a first height and any number of second rows can each have a second height that is smaller than the first height. The first rows of cells may include transistors with semiconductor nanoribbons having a first width and the second rows of cells may include transistors with semiconductor nanoribbons having a second width smaller than the first width. In some cases, any of the first rows of cells may also include transistors with semiconductor nanoribbons having the second width.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Sukru Yemenicioglu, Douglas Stout, Tai-Hsuan Wu, Xinning Wang, Ruth Brain, Chin-Hsuan Chen, Sivakumar Venkataraman, Quan Shi, Nikolay Ryzhenko Vladimirovich
  • Patent number: 12183682
    Abstract: A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Chen, Chien-Hsun Lee, Chung-Shi Liu, Jiun-Yi Wu, Shou-Yi Wang, Tsung-Ding Wang
  • Publication number: 20240429220
    Abstract: The invention provides a semiconductor structure, which comprises a first silicon substrate with a display region and a driving region defined thereon, a circuit layer located on the first silicon substrate, a plurality of light emitting elements located on the display region of the first silicon substrate, a driving chip located on the driving region of the first silicon substrate and electrically connected with the circuit layer, and a second silicon substrate located on the driving chip.
    Type: Application
    Filed: July 19, 2023
    Publication date: December 26, 2024
    Applicant: UNITED MICROELECTRONICS CORP
    Inventors: Chiu-Te Lee, Wen-Fang Lee, Shan-Shi Huang, Kuan-Chuan Chen
  • Patent number: 12176387
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
  • Patent number: 12169527
    Abstract: System and methods are directed to operations associated with an approximate nearest neighbor search engine. More specifically, a vector semantically representing content to be added to a search index may be received. The search index may include a neighborhood graph having a plurality of nodes, where each node of the plurality of nodes is associated with content in a content repository. A plurality of nodes within the search index determined to be most semantically similar to the received vector semantically representing content to be added to the search index may be identified. The node corresponding to the received vector semantically representing content to be added to the search index to the search index may be added to the search index and a listing of nearest neighbors associated with each of the of the plurality of nodes may be updated to include an identifier associated with the added node.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 17, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mingqin Li, Qi Chen, Jingdong Wang, Zengzhong Li, Jeffrey Song Zhu, Shi Zhang, Nilesh N. Yadav, Han Zhang
  • Publication number: 20240394484
    Abstract: A method, computer system, and a computer program product are provided for responding to a language input query with ad hoc enriched term data. The technique comprises extracting information relating to the language input query using a Language Support Assistance Service. The extracted information includes one or more language terms requiring further support and an associated request type. This is identified from metadata relating to the language input query. Information is provided to a Term Related Corpus Data Service that includes one or more language terms requiring further support and the identified request type and any identified sources. The Term Related Corpus Data Service returns one or more ad hoc enriched terms that are tailored to the one or more language terms requiring further support and is according to the associated request type. The Language Support Assistance Service provides a response to the language input query.
    Type: Application
    Filed: May 22, 2023
    Publication date: November 28, 2024
    Inventors: Jin Shi, CHIH-YUAN LIN, Shu-Chih Chen, PEI-YI LIN, Chao Yuan Huang
  • Publication number: 20240386744
    Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Chih Huang, Chih-Hua Chen, Yu-Jen Cheng, Chih-Wei Lin, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 12144065
    Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Da Cheng, Hsiu-Jen Lin, Cheng-Ting Chen, Wei-Yu Chen, Chien-Wei Lee, Chung-Shi Liu
  • Publication number: 20240371647
    Abstract: A semiconductor structure includes a die, a molding surrounding the die, and a polymer over the die and the molding. The die has a top surface. The molding has a top surface. The polymer has a first bottom surface contact the die and a second surface contacting the molding. The first bottom surface is at a level substantially same as the second bottom surface.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: YU-HSIANG HU, WEI-YU CHEN, HUNG-JUI KUO, WEI-HUNG LIN, MING-DA CHENG, CHUNG-SHI LIU
  • Patent number: 12122088
    Abstract: A production line for producing components to a high standard of cleanliness and sealed and protected in that state includes a loading device, a cleaning device, a detecting device, a pasting device, a heat-sealing device, a packing device, and transfer devices of the production line. The production line automatically processes the components for obtaining components with the high cleanliness. By the processes of protective film pasting, heat-sealing, and packing, the components may be further protected from subsequent pollution. A method for producing components with a high cleanliness applied to the production line is also disclosed.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: October 22, 2024
    Assignee: Fulian Yuzhan Precision Technology Co., Ltd
    Inventors: Jian-Wen Gao, Ting-Ting Li, Chu-Hui Wu, Ai-Jun Tang, Hui Wang, Shi Chen, Bo Yang, Feng Zhang, Kun-Liang Lin, Jian-Gang Zhang
  • Publication number: 20240346425
    Abstract: The present disclosure provides a visual analysis system based on a discipline assessment report, and relates to the technical field of discipline assessment. The visual analysis system based on a discipline assessment report includes a data acquisition unit. An output end of the data acquisition unit is electrically connected to an input end of a data preprocessing unit, and an output end of the data preprocessing unit is electrically connected to an input end of a central processing unit. According to the visual analysis system based on a discipline assessment report, development and changes of the discipline in a project corresponding to the indicator are accurately determined, and a clear plan and development goal are made for overall development of the discipline. Therefore, the overall discipline assessment and a follow-up development process are more clear and distinct.
    Type: Application
    Filed: September 27, 2022
    Publication date: October 17, 2024
    Inventors: QINGSONG WU, YINGCONG ZHANG, MING MA, CAN XIANG, SHI CHEN, JIANCAI WU, YANG JIN, ZHENG WANG, FEI LUO, ZHIHUI WANG
  • Patent number: 12119229
    Abstract: A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing a molding surrounding the die; removing the sacrificial layer from the die; disposing a polymer over the die and the molding, wherein the polymer has a first bottom surface contacting the die and a second bottom surface contacting the molding, and the first bottom surface is at a level substantially same as the second bottom surface.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hsiang Hu, Wei-Yu Chen, Hung-Jui Kuo, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 12116415
    Abstract: Provided are antibodies that recognize the B-Cell Maturation Antigen (BCMA) and methods of use thereof.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: October 15, 2024
    Assignees: Single Cell Technology, Inc., ACROBiosystems, Inc.
    Inventors: Leyan Tang, Allison Schulkins, Kimberly Than, Chun-Nan Chen, Jingyun Miao, Xiaohui Zhang, Xiaojuan Shi, Lin Zhang
  • Patent number: 12119238
    Abstract: A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Wei-Hung Lin, Kuei-Wei Huang, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20240325520
    Abstract: The present invention discloses a recombinant RBD trimer protein capable of simultaneously generating cross neutralization activity for various severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) epidemic strains. The RBD trimer protein is taken as an antigen and supplemented with an adjuvant to immunize an organism, so that a high-titer neutralizing antibody aiming at various SARS-CoV-2 epidemic strains can be generated at the same time, and the antibody has a certain broad-spectrum property and can be used for treating and/or preventing SARS-CoV-2 infection and/or coronavirus disease 2019.
    Type: Application
    Filed: September 24, 2021
    Publication date: October 3, 2024
    Inventors: Qiming LI, Yu LIANG, Jing ZHANG, Jiguo SU, Zibo HAN, Shuai SHAO, Yanan HOU, Hao ZHANG, Shi CHEN, Yuqin JIN, Xuefeng ZHANG, Lifang DU, JunWei HOU, Zhijing MA, Zehua LEI, Fan ZHENG, Fang TANG, Zhaoming LIU, Ning LIU
  • Patent number: D1052696
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: November 26, 2024
    Assignee: Globe Union Industrial Corp.
    Inventors: Yi-Shan Chiang, Ya-Chieh Lai, Chun-Yi Tu, Shi-Chen Lai, Meng-Chun Yen
  • Patent number: D1056138
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: December 31, 2024
    Assignee: Globe Union Industrial Corp.
    Inventors: Yi-Shan Chiang, Ya-Chieh Lai, Chun-Yi Tu, Shi-Chen Lai, Meng-Chun Yen
  • Patent number: D1057096
    Type: Grant
    Filed: July 14, 2023
    Date of Patent: January 7, 2025
    Assignee: GLOBE UNION INDUSTRIAL CORP.
    Inventors: Yi-Shan Chiang, Ya-Chieh Lai, Chun-Yi Tu, Shi-Chen Lai, Meng-Chun Yen