Patents by Inventor Shi-Cheng Lin

Shi-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240112959
    Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Kuan-Ting PAN, Zhi-Chang LIN, Yi-Ruei JHAN, Chi-Hao WANG, Huan-Chieh SU, Shi Ning JU, Kuo-Cheng CHIANG
  • Publication number: 20240096895
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Patent number: 8017175
    Abstract: A highly stable, multilayer organic molecular photoelectric element without interlayer miscibility phenomenon during manufacturing process, and a method for producing multilayer organic molecular photoelectric elements with simplified solution process are disclosed.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: September 13, 2011
    Assignee: National Chiao Tung University
    Inventors: Hsin-Fei Meng, Sheng-Fu Horng, Chain-Shu Hsu, Shi-Cheng Lin, Hua-Hsien Liao
  • Patent number: 7524732
    Abstract: A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the sidewall of the shallow trench isolation structure, and further comprises a first insulating layer and an L-shape second insulating layer spacer, wherein the first insulating layer is located between the L-shape second insulating layer spacer and the substrate. The tunnel insulating layer is located on the substrate of the active area and connects to the first insulating layer of the composite spacer on its corresponding side.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: April 28, 2009
    Assignee: Promos Technologies Inc.
    Inventors: Chung-We Pan, Shi-Cheng Lin, Ching-Hung Fu, Chih-Ping Chung
  • Publication number: 20070272962
    Abstract: A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the sidewall of the shallow trench isolation structure, and further comprises a first insulating layer and an L-shape second insulating layer spacer, wherein the first insulating layer is located between the L-shape second insulating layer spacer and the substrate. The tunnel insulating layer is located on the substrate of the active area and connects to the first insulating layer of the composite spacer on its corresponding side.
    Type: Application
    Filed: August 21, 2006
    Publication date: November 29, 2007
    Applicant: PROMOS TECHNOLOGIES INC.
    Inventors: Chung-We Pan, Shi-Cheng Lin, Ching-Hung Fu, Chih-Ping Chung
  • Publication number: 20070111006
    Abstract: A highly stable, multilayer organic molecular photoelectric element without interlayer miscibility phenomenon during manufacturing process, and a method for producing multilayer organic molecular photoelectric elements with simplified solution process are disclosed.
    Type: Application
    Filed: December 20, 2005
    Publication date: May 17, 2007
    Inventors: Hsin-Fei Meng, Sheng-Fu Horng, Chain-Shu Hsu, Shi-Cheng Lin, Hua-Hsien Liao