Abstract: A strip light switch includes an insulative housing with terminal grooves and positioning grooves defined in an accommodation chamber therein, a terminal set including at least one first terminal, at least one second terminal and multiple third terminals mounted in the terminal grooves and multiple mating connection terminals detachably mounted in the positioning grooves in a replaceable manner for conduction with the third terminals, a conductive shrapnel mounted in the accommodation chamber, and a press device including a cylindrical press block supported on the conductive shrapnel pressable by a user to force the conductive shrapnel in conducting the first and second terminals, conducting plates mounted in the cylindrical press block and disposed in contact with the conducting plates of the mating connection terminal and a light-emitting component mounted in the cylindrical press block for electrical contact with the conducting plates.

Abstract: A strip light switch includes an insulative housing with terminal grooves and positioning grooves defined in an accommodation chamber therein, a terminal set including at least one first terminal, at least one second terminal and multiple third terminals mounted in the terminal grooves and multiple mating connection terminals detachably mounted in the positioning grooves in a replaceable manner for conduction with the third terminals, a conductive shrapnel mounted in the accommodation chamber, and a press device including a cylindrical press block supported on the conductive shrapnel pressable by a user to force the conductive shrapnel in conducting the first and second terminals, conducting plates mounted in the cylindrical press block and disposed in contact with the conducting plates of the mating connection terminal and a light-emitting component mounted in the cylindrical press block for electrical contact with the conducting plates.

Abstract: A method for fabricating dielectric isolated silicon islands or regions is described in this invention. A hard composite mask of pad oxide and silicon nitride is first patterned on a silicon substrate and trenches of required dimensions are etched into silicon. After forming an oxide liner on trench surfaces, boron ions are implanted in areas around the trenches such that heavily doped p+ regions are formed. The oxide liner is anisotropically etched with a reactive ion etching process such that only the silicon surface at trench bottom is exposed, leaving the oxide liner on trench walls. Epitaxial silicon is then deposited selectively on exposed single crystal silicon surface so as to fill the trenches. After removing the hard mask, trenches are masked with photo-resist pattern and the wafer is anodically etched in an aqueous bath of HF to form a buried porous silicon layer under and around the trenches. After removing the mask, the porous silicon is then oxidized.

Abstract: A thrust pad assembly which is capable of reducing the quantity of metal electroplated onto the edge region of a substrate to eliminate or reduce the need for edge bevel cleaning or removal of excess metal from the substrate after the electroplating process. The thrust pad assembly includes an air platen through which air is applied at variable pressures to the central and edge regions, respectively, of a thrust pad. The thrust pad applies pressure to a contact ring connected to an electroplating voltage source. The contact ring applies relatively less pressure to the edge region than to the central region of the substrate, thereby reducing the ohmic contact.

Abstract: A method for fabricating dielectric isolated silicon islands or regions is described in this invention. A hard composite mask of pad oxide and silicon nitride is first patterned on a silicon substrate and trenches of required dimensions are etched into silicon. After forming an oxide liner on trench surfaces, boron ions are implanted in areas around the trenches such that heavily doped p+ regions are formed. The oxide liner is anisotropically etched with a reactive ion etching process such that only the silicon surface at trench bottom is exposed, leaving the oxide liner on trench walls. Epitaxial silicon is then deposited selectively on exposed single crystal silicon surface so as to fill the trenches. After removing the hard mask, trenches are masked with photo-resist pattern and the wafer is anodically etched in an aqueous bath of IF to form a buried porous silicon layer under and around the trenches. After removing the mask, the porous silicon is then oxidized.