Abstract: A self-regulating ramp up circuit generates a high voltage signal having a slow, smooth ramp up and reduced process and temperature variation. The circuit uses a resistor and a capacitor to control the rate at which the output signal changes state. In one embodiment, an enable signal operating at a low voltage level is shifted to the desired high voltage level using a level shifter. The resulting value is inverted using an inverter operating at the high voltage level and having a resistor in the pulldown path. The circuit output node is coupled to the output node of the inverter through a capacitor, and to the high voltage power supply through a pullup gated by the output node of the inverter. In some embodiments, the ramp up circuit forms a portion of a programmable logic device (PLD), and the capacitor and/or resistor have programmable capacitance/resistance values.

Abstract: An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.

Abstract: An input driver circuit for accommodating a plurality of input/output voltage standards is provided. The input driver circuit employs an adjustable trip point that can be calibrated for multiple input voltage standards. The adjustable trip point is provided by a trigger circuit. A control circuit determines whether the trigger circuit is on or off by comparing a configuration input thereof with a reference power supply input thereof. When the trigger circuit is on, the trip point is active during a low to high transition of the signal input.

Abstract: An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.

Abstract: A scalable pterm generator provides enhanced programming flexibility in logic devices such as PLAs. A scalable pterm generator includes both wide AND logic and alternative OR logic that enables efficient implementation of functions not requiring the full wide AND logic. According to an embodiment of the invention, a scalable pterm generator comprises a wide AND gate, an alternative logic circuit, and an output control circuit. The alternative logic circuit includes OR logic, thereby providing an alternative to the pure AND functionality of the wide AND gate. A set of logic input lines connects to both the inputs of the wide AND gate and the inputs of the alternative logic circuit. An output control circuit selects the final output of the scalable pterm generator. According to an embodiment of the invention, the output control circuit comprises a programmable circuit. According to another embodiment of the invention, the output control circuit comprises a multiplexer.

Abstract: A power-on reset (POR) circuit that delays de-assertion a POR control signal in an IC device such that, when unstable power levels are detected, the POR control signal is maintained in an asserted condition until the IC device is fully reset. During a start-up phase of the IC device operation, the POR control circuit maintains the POR control signal in the asserted condition for a delay period whose length is determined, in part, by the amount of noise in the applied power. After the internal voltage of the IC device achieves a steady state for a suitable period of time, the POR control circuit de-asserts the POR control signal, thereby initiating configuration of the IC device. Subsequently, if a low power condition is detected, the POR control circuit asserts the POR control signal, and maintains the POR control signal in the asserted condition for a pre-defined delay period after the low-power event is detected, thereby allowing the IC device to fully reset.

Abstract: A ramping circuit gradually applies an erasing voltage to a memory cell. Within the ramping circuit an NMOS transistor is disclosed which gradually supplies the erasing voltage to the memory cell in response to an external ramping voltage. The NMOS transistor supplies the erasing voltage until the loss voltage of the transistor limits a maximum erasing voltage that the NMOS transistor can supply. The specification then discloses a PMOS transistor which operates to supply the erasing voltage to the memory cell when the NMOS transistor can no longer do so. The PMOS transistor is connected to control circuitry which keeps the PMOS transistor inactive until the output voltage of the NMOS transistor is limited by its voltage loss.

Abstract: A ramping circuit gradually applies an erasing voltage to a memory cell. Within the ramping circuit an NMOS transistor is disclosed which gradually supplies the erasing voltage to the memory cell in response to an external ramping voltage. The NMOS transistor supplies the erasing voltage until the body effect loss voltage of the transistor limits a maximum erasing voltage that the NMOS transistor can supply. The specification then discloses a PMOS transistor which operates to supply the erasing voltage to the memory cell when the NMOS transistor can no longer do so. The PMOS transistor is connected to control circuitry which keeps the PMOS transistor inactive until the output voltage of the NMOS transistor is limited by its body effect voltage loss.

Abstract: The present invention provides a logic circuit that is programmable to implement a first logic function or a second logic function using as few as four transistors. In one embodiment, the logic circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first signal line for receiving a first input signal, a second signal line for receiving a second input signal, a control signal line for receiving a control signal, and an output signal line for receiving an output signal. The first transistor and the second transistor are connected in series between the control signal line and the output signal line. The third transistor is connected in series between the first input signal line and the output signal line. The fourth transistor is connected in series between the second input signal line and the output signal line.

Abstract: A balanced truth-and-complement circuit. A driver circuit which generates a signal and its complement in response to an input signal; a switching circuit selects between the signal and its complement in response to external control signals; and a sense amplifier detects and amplifies the signal selected by the switching circuit. The driver circuit has NMOS transistors and inverters arranged so as to connect either the signal or its complement to the switching circuit.

Abstract: A voltage regulator for a charge pump is provided with two input paths from a reference input voltage to a comparator, each path having a node between a capacitor pair. The two paths are alternately initialized and used to control the charge pump which generates a reference output voltage, so that the reference output voltage tracks the reference input voltage at all times. Each path has its own capacitor divider and switching circuitry to alternately connect the nodes between the respective pairs of capacitors to the comparator, which compares the nodes to a second voltage reference. Since the circuit is alternately initialized, any alterations to the voltage introduced at the nodes between each of the two capacitor pairs, are corrected to the proper level within a short time.

Abstract: A power-on reset (POR) circuit including a first single-level POR, a second single-level POR, a combining circuit, and a latch. Responsive to the voltage on a voltage supply terminal, the first single-level POR generates a first reset signal which terminates at a first trigger level voltage, and the second single-level POR generates a second reset signal which terminates at a second trigger level voltage. A combining circuit logically combines the first and second reset signals, and generates a combined output signal. This output signal controls a latch which provides the POR signal. When the supply voltage is below both trigger levels a POR signal is generated. When the supply voltage is above both trigger levels, no POR signal is generated. When the supply voltage is between trigger levels of the two POR circuits, the combining circuit leaves a floating output signal. Thus the latch does not switch.

Abstract: A selectable inverter circuit. An inverter circuit receives an input signal which is complemented before becoming an output signal. A pass-through circuit for setting the output signal equivalent to the input signal. An enabling circuit for providing power to the inverter circuit, in response to a selection signal. The enabling circuit also provides a charge storing circuit with a supplemental charge. The charge storing circuit releasing the supplemental charge to the inverter circuit, and so provides the inverter circuit with even more power. The enabling circuit activating the pass-through circuit and deactivating the inverter circuit in response to the first state of the selection signal. The enabling circuit deactivating the pass-through circuit and activating the inverter circuit in response to the second state of the selection signal.