Abstract: An integrated circuit includes a main clock tree, a reference clock trunk, a reference clock buffer and a calibration circuit. The main clock tree transmits a main operation clock to an internal node via serially-coupled buffers to form a local clock at an internal node. The reference clock buffer transmits a main reference clock via the reference clock trunk to form a reference clock at a terminal node. The calibration circuit compares phases of the local clock and the reference clock to accordingly generate a control signal, so the main clock tree can adjust phase of the local clock according to the control signal.

Abstract: An aging detection circuit is provided. The aging detection circuit is configured on a chip and includes a testing circuit and an aging signal generation circuit. The testing circuit is electrically coupled to the aging signal generation circuit. The testing circuit generates an output signal. The aging signal generation circuit includes a signal generation circuit and a selection circuit. The signal generation circuit generates multiple input signals having different frequencies. The selection circuit selectively outputs one of the input signals as an aging signal to an input terminal of the testing circuit or feeds back the output signal generated by the testing circuit to the input terminal of the testing circuit.

Abstract: A method for determining performance of an integrated circuit (IC) is disclosed herein. The method includes following operations: disposing hardware performance monitors (HPMs) in each of ICs, in which each of HPMs generates a value for generating the performance of the IC; providing a performance function including of terms according to values generated by the HPMs, in which a weight is associated with each of terms; determining the weight of each of terms according to a first set of ICs of the ICs, wherein the performance of each of the ICs is known; and determining the performance of a first ICs of the ICs according to the performance function, wherein the performance function and the weights are built into the first ICs.

Abstract: Method for input/output (IO) design of a chip, including: according to a signal IO pin sequence and associated driving parameters, sequentially placing a signal IO cell in the IO design associated with each of the signal IO pins; after a signal IO cell is placed, performing a simultaneous switching output (SSO) verification step according to physical layout parameters and locations of the signal IO cells placed in the IO design, so as to check whether an SSO specification is violated; if not violated, continuing to place a signal IO cell of a next signal IO pin; if violated, including a decoupling capacitor, an IO power cell and/or an IO ground cell in the IO design.

Abstract: The present invention discloses an efficient method to determine the performance of an integrated circuit or a chip by instantiating a plurality of HPM in the integrated circuit to generate the performance of the integrated circuit according to a performance function, wherein each term of the performance function is based on the values of the HPM(s) and the weighting of the term is determined through machine leaning, so that the performance of each chip can be determined by the performance function.

Abstract: Method for input/output (IO) design of a chip, including: according to a signal IO pin sequence and associated driving parameters, sequentially placing a signal IO cell in the IO design associated with each of the signal IO pins; after a signal IO cell is placed, performing a simultaneous switching output (SSO) verification step according to physical layout parameters and locations of the signal IO cells placed in the IO design, so as to check whether an SSO specification is violated; if not violated, continuing to place a signal IO cell of a next signal IO pin; if violated, including a decoupling capacitor, an IO power cell and/or an IO ground cell in the IO design.

Abstract: The present invention discloses a power booting sequence control system and the control method thereof, which optimizes a power booting sequence of a plurality of power switches in an integrated circuit. An initial module initializes a target charge value, a preset current budget and a plurality of time intervals. A current lookup module obtains a booting current across a power switch from a built-in current lookup table. A first computing unit and a second computing unit compute a first and a second power switch numbers respectively. A processing module selects the small number of the first and the second power switch number to get a maximum number of power booting switches under the time intervals, and opens the maximum number of the power booting switches. Therefore, the system keeps the in-rush current value under the preset current budget and speeds up the ramp-up time in a power booting state.

Abstract: Circuits and methods for providing control of a power up sequence for supplying a gated power supply to a circuit portion. A power switch fabric is provided having more than two chains with more than two bits of control. The chains include power switches that are sequentially enabled in response to control signal to supply a virtual power supply to a gated circuit to support power gating. The power switches may include daughter switches and mother switches, where the mother switches are enabled later in time than the daughter switches. The enable signals to allow the virtual power supply to begin powering up may be timed to control the ramp up time, in rush current and peak current during the power up sequence of the virtual power supply. Methods for providing timing for the daughter and mother switches and enables to multiple chains in a power switch fabric are disclosed.

Abstract: The present invention discloses a power booting sequence control system and the control method thereof, which optimizes a power booting sequence of a plurality of power switches in an integrated circuit. An initial module initializes a target charge value, a preset current budget and a plurality of time intervals. A current lookup module obtains a booting current across a power switch from a built-in current lookup table. A first computing unit and a second computing unit compute a first and a second power switch numbers respectively. A processing module selects the small number of the first and the second power switch number to get a maximum number of power booting switches under the time intervals, and opens the maximum number of the power booting switches. Therefore, the system keeps the in-rush current value under the preset current budget and speeds up the ramp-up time in a power booting state.

Abstract: An automatically configurable power control unit (PCU) is described that can be configured and used to satisfy requirements of different power domain of an integrated circuit. When implemented the PCU is automatically configured into a power control manager (PCM) along with other PCU's used with additional power domains in the integrated circuit. The PCM dispatches power on and off commands to each PCU contained within the PCM, schedules power on and off sequences amongst a plurality of PCU controlled by the PCM, blocks inappropriate power mode commands and monitors the state of each power domain coupled to the various PCU controlled by the PCM.

Abstract: In one embodiment, a power domain isolation interface is disclosed. The interface has a level shifter having a signal input coupled to a first power domain and a memory element. The memory element has a signal input coupled to an output of the level shifter, an output coupled to a second power domain, and a hold enable input, wherein the memory element is configured to hold an input state when the hold enable input becomes asserted.

Abstract: Circuits and methods for providing control of a power up sequence for supplying a gated power supply to a circuit portion. A power switch fabric is provided having more than two chains with more than two bits of control. The chains include power switches that are sequentially enabled in response to control signal to supply a virtual power supply to a gated circuit to support power gating. The power switches may include daughter switches and mother switches, where the mother switches are enabled later in time than the daughter switches. The enable signals to allow the virtual power supply to begin powering up may be timed to control the ramp up time, in rush current and peak current during the power up sequence of the virtual power supply. Methods for providing timing for the daughter and mother switches and enables to multiple chains in a power switch fabric are disclosed.