Abstract: A driving circuit controlling a voltage level of an input/output pad and having an electrostatic discharge (ESD) protection function comprises a detector, a controller, and a release control element. The detector is configured to couple to a power terminal and the input/output pad. The controller is coupled to the detector. The release control element is coupled to the power terminal or the input/output pad and coupled to the controller. When an ESD event occurs at the power terminal or the input/output pad, the detector activates the controller to a control signal to control the voltage level of the input/output pad.

Abstract: A method for fabricating a bonding pad structure includes forming a dielectric layer on a substrate; forming a first metal pattern layer in the dielectric layer. The first metal pattern layer includes a first body portion having a plurality of first openings in a central region of the first body portion and a plurality of second openings arranged along a peripheral region of the first body portion and surrounding the plurality of first openings; and a plurality of first island portions correspondingly disposed in the plurality of second openings and spaced apart from the first body portion. The method further includes forming a plurality of first interconnect structures in the dielectric layer and corresponding to the plurality of first island portions; and forming a bonding pad on the dielectric layer and directly above the first metal pattern layer.

Abstract: A method for fabricating a bonding pad structure includes forming a dielectric layer on a substrate; forming a first metal pattern layer in the dielectric layer. The first metal pattern layer includes a first body portion having a plurality of first openings in a central region of the first body portion and a plurality of second openings arranged along a peripheral region of the first body portion and surrounding the plurality of first openings; and a plurality of first island portions correspondingly disposed in the plurality of second openings and spaced apart from the first body portion. The method further includes forming a plurality of first interconnect structures in the dielectric layer and corresponding to the plurality of first island portions; and forming a bonding pad on the dielectric layer and directly above the first metal pattern layer.

Abstract: A bonding pad structure is provided. The structure includes a dielectric layer on a substrate. A bonding pad is disposed on the dielectric layer and a first metal pattern layer is embedded in the dielectric layer and directly below the bonding pad. The first metal pattern layer includes a first body portion and first island portions. The first body portion has first openings in a central region of the first body portion and second openings arranged along a peripheral region of the first body portion and surrounding the first openings. The first island portions are correspondingly disposed in the second openings and spaced apart from the first body portion. First interconnect structures are disposed in the dielectric layer and correspond to the first island portions, such that the bonding pad is electrically connected to the first island portions.

Abstract: A driving circuit controlling a voltage level of an input/output pad and having an electrostatic discharge (ESD) protection function comprises a detector, a controller, and a release control element. The detector is configured to couple to a power terminal and the input/output pad. The controller is coupled to the detector. The release control element is coupled to the power terminal or the input/output pad and coupled to the controller. When an ESD event occurs at the power terminal or the input/output pad, the detector activates the controller to a control signal to control the voltage level of the input/output pad.

Abstract: An analog-to-digital converter (ADC) for converting an optical signal into an electrical signal is disclosed. The ADC includes a detection module, a first P-type metal oxide semiconductor (PMOS) transistor, a first N-type metal oxide semiconductor (NMOS) transistor, a first switch unit, and an output module. The first PMOS transistor and the first NMOS transistor form an inverter. The first switch unit is disposed between the input terminal and the output terminal of the inverter and is turned on/off according to a first control signal. The output module is coupled to the output terminal of the inverter for counting the time that an input voltage is greater than a reference voltage and generating a digital signal.

Abstract: A liquid crystal display driving circuit is provided. The liquid crystal display driving circuit includes a front driving stage and a plurality of serially connected subsequent driving stages. The front driving stage receives a first trigger pulse and a second trigger pulse consecutively in a testing operation. The serially connected subsequent driving stages coupled to the front driving stage such that the output terminal of each driving stage is electrically connected to the input terminal of the following driving stage as well as the input terminal of the one after. The output terminal of the front driving stage is electrically connected to the input terminal of first subsequent driving stage and the one immediately thereafter.

Abstract: A negative voltage converter includes six transistors. A first end and a control end of a first transistor are coupled to a signal input. A first end of a second transistor is coupled to the signal input, and a control end of which is coupled to a first clock and the first transistor. A first end of a third transistor is coupled to the signal input, a control end of the third transistor is coupled with a second clock and the second transistor. A first end of a fourth transistor is coupled to the second end of the third transistor, a control end of which is coupled with the first clock and the third transistor. A first end of a fifth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the second clock and the fourth transistor A first end of a sixth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the first clock and the fifth transistor.

Abstract: A shift register circuit which having a plurality of stages, a signal of the timing controller is conveyed to the shift register circuit for generating and transferring a sample signal to data latch circuit. The first stage of the shift register, comprising a disable circuit and a sample circuit, receives the signal of the timing controller and transfers a right sample signal to the data latch circuit and next stage of the shift register. The disable circuit of first stage of the shift register receives sample signal of second stage of the shift register to stop the sampling procedure of the first stage of the shift register.

Abstract: An analog-to-digital converter (ADC) for converting an optical signal into an electrical signal is disclosed. The ADC includes a detection module, a first P-type metal oxide semiconductor (PMOS) transistor, a first N-type metal oxide semiconductor (NMOS) transistor, a first switch unit, and an output module. The first PMOS transistor and the first NMOS transistor form an inverter. The first switch unit is disposed between the input terminal and the output terminal of the inverter and is turned on/off according to a first control signal. The output module is coupled to the output terminal of the inverter for counting the time that an input voltage is greater than a reference voltage and generating a digital signal.

Abstract: A negative voltage converter includes six transistors. A first end and a control end of a first transistor are coupled to a signal input. A first end of a second transistor is coupled to the signal input, and a control end of which is coupled to a first clock and the first transistor. A first end of a third transistor is coupled to the signal input, a control end of the third transistor is coupled with a second clock and the second transistor. A first end of a fourth transistor is coupled to the second end of the third transistor, a control end of which is coupled with the first clock and the third transistor. A first end of a fifth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the second clock and the fourth transistor A first end of a sixth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the first clock and the fifth transistor.

Abstract: A display driving circuit having a plurality of driving stages and driving lines is provided. The driving stages are electrically coupled in serial, and each of the driving stages comprises a conducting path for transmitting an electric signal from the previous driving stage to the next driving stage via the current driving stage. Each of the driving lines respectively corresponds to a driving stage and electrically connects to an output terminal of the corresponding driving stage. The display driving circuit is characterized in that a redundant device is only installed in one part of the driving stages. The redundant device is capable of supplying an extra conducting path to transmit an electric signal from the previous driving stage to the next driving stage via the current driving stage while the original conducting path in the corresponding driving stage is broken.

Abstract: A signal transmitting system comprising a signal outputting unit and a signal receiving unit is provided. The signal outputting unit receives a first signal and outputs a second signal. The signal receiving unit receives the second signal and outputs a third signal. The signal outputting unit comprises an inverting device which receives the first signal and outputs a first inverted signal, and a signal driving device which receives the first inverted signal and outputs the second signal. The signal driving device comprises two NMOS transistors. The first NMOS transistor has a drain biased by a first voltage, and a gate receiving a control signal. The second NMOS transistor has a gate receiving the first inverted signal, a source biased by a second voltage, and a drain electronically coupled to the source of the first transistor. The drain of the second NMOS transistor outputs the second signal.

Abstract: A shift register circuit which having a plurality of stages, a signal of the timing controller is conveyed to the shift register circuit for generating and transferring a sample signal to data latch circuit. The first stage of the shift register, comprising a disable circuit and a sample circuit, receives the signal of the timing controller and transfers a right sample signal to the data latch circuit and next stage of the shift register. The disable circuit of first stage of the shift register receives sample signal of second stage of the shift register to stop the sampling procedure of the first stage of the shift register.

Abstract: A liquid crystal display driving circuit is provided. The liquid crystal display driving circuit includes a front driving stage and a plurality of serially connected subsequent driving stages. The front driving stage receives a first trigger pulse and a second trigger pulse consecutively in a testing operation. The serially connected subsequent driving stages coupled to the front driving stage such that the output terminal of each driving stage is electrically connected to the input terminal of the following driving stage as well as the input terminal of the one after. The output terminal of the front driving stage is electrically connected to the input terminal of first subsequent driving stage and the one immediately thereafter.

Abstract: A liquid crystal display driving circuit, verifying apparatus and error tolerance method is disclosed. The liquid crystal display driving circuit has a plurality of driving stages each having a plurality of verifying apparatus, a logic operation unit and a driving switch. Each verifying apparatus comprises a storage unit, a data switch and an edge detector. The storage unit receives a first and a second trigger pulse during a first and a second time period and then outputs a first and a second shifted signal that correspond to the first and the second triggered pulse submitted to the storage unit. The first and the second shifted signal are transferred to a first and a second output path through switching the data switch during the first and the second time period. The edge detector receives the first shifted signal and set the second output path to a pre-defined logic potential during the second time period if no edge transition is detected during the first time period.

Abstract: A signal transmitting system comprising a signal outputting unit and a signal receiving unit is provided. The signal outputting unit receives a first signal and outputs a second signal. The signal receiving unit receives the second signal and outputs a third signal. The signal outputting unit comprises an inverting device which receives the first signal and outputs a first inverted signal, and a signal driving device which receives the first inverted signal and outputs the second signal. The signal driving device comprises two NMOS transistors. The first NMOS transistor has a drain biased by a first voltage, and a gate receiving a control signal. The second NMOS transistor has a gate receiving the first inverted signal, a source biased by a second voltage, and a drain electronically coupled to the source of the first transistor. The drain of the second NMOS transistor outputs the second signal.

Abstract: A shift register having a plurality of cascaded shift register stages. The shift register is controlled by a first and a second clock signal being out of phase. Each shift register stage includes an input unit, an output unit, and a control unit. The input unit outputs a first signal according to the first clock signal. The output unit outputs an output signal according to the first signal. The control unit is coupled to the input and output units and controls the output unit according to the first and output signals, thereby stabilizing the state of the output signal.

Abstract: A liquid crystal display driving circuit, verifying apparatus and error tolerance method is disclosed. The liquid crystal display driving circuit has a plurality of driving stages each having a plurality of verifying apparatus, a logic operation unit and a driving switch. Each verifying apparatus comprises a storage unit, a data switch and an edge detector. The storage unit receives a first and a second trigger pulse during a first and a second time period and then outputs a first and a second shifted signal that correspond to the first and the second triggered pulse submitted to the storage unit. The first and the second shifted signal are transferred to a first and a second output path through switching the data switch during the first and the second time period. The edge detector receives the first shifted signal and set the second output path to a pre-defined logic potential during the second time period if no edge transition is detected during the first time period.

Abstract: A bi-directional shift-register circuit for outputting data in different turns and reducing the power loss according to a low-voltage clock signal, a first directional signal, and a second directional signal.