Abstract: A junction-free NAND flash memory is described, including a substrate, memory cells, source/drain inducing (SDI) gates electrically connected with each other, and a dielectric material layer. The memory cells are disposed on the substrate, wherein each memory cell includes a charge storage layer. Each SDI gate is disposed between two neighboring memory cells. The dielectric material layer is disposed between the memory cells and the SDI gates and between the SDI gates and the substrate.

Abstract: A junction-free NAND flash memory is described, including a substrate, memory cells, source/drain inducing (SDI) gates electrically connected with each other, and a dielectric material layer. The memory cells are disposed on the substrate, wherein each memory cell includes a charge storage layer. Each SDI gate is disposed between two neighboring memory cells. The dielectric material layer is disposed between the memory cells and the SDI gates and between the SDI gates and the substrate.

Abstract: A non-volatile memory having a memory cell formed on a substrate is provided. A trench is formed in the substrate. The memory cell has a first gate, a second gate, a charge storage layer, a first source/drain region and a second source/drain region. The first gate is disposed in the trench of the substrate. The second gate is disposed on the substrate at one side of the trench. The charge storage layer is disposed between the first gate and the substrate and between the second gate and the substrate. The first source/drain region is disposed in the substrate at the bottom of the trench. The second source/drain region is disposed in the substrate at one side of the second gate.

Abstract: A non-volatile memory is provided. At least two bit lines are disposed in a substrate. The two bit lines are arranged in parallel and extend in a first direction. A plurality of select gate structures is disposed on the substrate between the two bit lines respectively. The select gate structures are arranged in parallel and extend in a first direction. A gap is disposed between each two neighboring select gate structures. A plurality of control gate lines is disposed on the substrate and fills in the gaps between two neighboring select gate structures respectively. The control gate lines are arranged in parallel and extend in a second direction, which crosses the first direction. A plurality of charge storage layers is disposed between the select gate structures and control gate lines respectively.