Abstract: A method that determines the system impact of single event upset (SEU) and a single event upset (SEU) wrapper that controls a SEU controller is disclosed. The method injects faults into a component (e.g. FPGA, ASIC) of an operational system that is carrying live traffic and monitors the system's response to the faults to determine the impact of SEU on the system. The SEU wrapper sends the SEU controller a pattern scheme that includes information indicating when, where, how often, and/or how long to inject bursts of one or more faults into memory of the component of the system. A burst of faults contains faults that are consecutively injected into the array of memory blocks. After each fault in a burst is injected, one or more errors in one or more memory elements are detected and/or corrected. Information regarding the detection and/or the correction of an error is updated using registers that store counters. After injecting a burst of faults, the SEU controller waits for a predetermined amount of time.

Abstract: A method that determines the system impact of single event upset (SEU) and a single event upset (SEU) wrapper that controls a SEU controller is disclosed. The method injects faults into a component (e.g. FPGA, ASIC) of an operational system that is carrying live traffic and monitors the system's response to the faults to determine the impact of SEU on the system. The SEU wrapper sends the SEU controller a pattern scheme that includes information indicating when, where, how often, and/or how long to inject bursts of one or more faults into memory of the component of the system. A burst of faults contains faults that are consecutively injected into the array of memory blocks. After each fault in a burst is injected, one or more errors in one or more memory elements are detected and/or corrected. Information regarding the detection and/or the correction of an error is updated using registers that store counters. After injecting a burst of faults, the SEU controller waits for a predetermined amount of time.

Abstract: Disclosed are transition metal electrodes for electrochemical cells using gel-state and solid-state polymers. The electrodes are suitable for use in primary and secondary cells. The electrodes (either negative electrode or positive electrode) are characterized by uniform dispersion of the transition metal at the nanoscale in the polymer. The transition metal moiety is structurally amorphous, so no capacity fade should occur due to lattice expansion/contraction mechanisms. The small grain size, amorphous structure and homogeneous distribution provide improved charge/discharge cycling performance, and a higher initial discharge rate capability. The cells can be cycled at high current densities, limited only by the electrolyte conductivity. A method of making the electrodes (positive and negative), and their usage in electrochemical cells are disclosed.