Patents by Inventor Shi Ning Ju

Shi Ning Ju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11380591
    Abstract: Methods for manufacturing semiconductor structures are provided. The method includes alternately stacking sacrificial layers and semiconductor layers over a substrate to form a semiconductor stack and forming a first mask structure and a second mask structure over the semiconductor stack. In addition, a width of the first mask structure is substantially equal to a width of the second mask structure. The method further includes forming spacers on sidewalls of the second mask structure and patterning the semiconductor stack to form a first fin structure overlapping the first mask structure and a second fin structure overlapping the second mask structure and the spacers. In addition, the first fin structure has a first width and the second fin structure has a second width different from the first width. The method further includes removing the sacrificial layers to form first nanostructures and second nanostructures.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11362213
    Abstract: A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 11362001
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure formed over a substrate. The semiconductor structure further includes first nanostructures, second nanostructures, third nanostructures, and fourth nanostructures. The semiconductor structure further includes a first gate structure wrapping around the first nanostructures and the second nanostructures, and a second gate structure wrapping around the third nanostructures and the fourth nanostructures. In addition, a first lateral distance between the first fin structure and the second fin structure is shorter than a second lateral distance between the third fin structure and the fourth fin structure, and the first fin structure and the second fin structure are narrower than the third fin structure and the fourth fin structure.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Han Liu, Chih-Hao Wang, Kuo-Cheng Chiang, Shi-Ning Ju, Kuan-Lun Cheng
  • Publication number: 20220181259
    Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 9, 2022
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang
  • Patent number: 11355601
    Abstract: A semiconductor structure includes a source feature, a drain feature, one or more channel layers connecting the source feature and the drain feature, and a gate structure between the source feature and the drain feature. The gate structure engages each of the one or more channel layers. The semiconductor structure further includes a first source silicide feature over the source feature, a source contact over the first source silicide feature, a second source silicide feature under the source feature, a via under the second source silicide feature, and a power rail under the via. The first and the second source silicide features fully surround the source feature in a cross-sectional view. The power rail is a backside power rail.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang, Cheng-Chi Chuang
  • Patent number: 11355396
    Abstract: The present disclosure provides a method of forming a semiconductor structure with a metal gate. The semiconductor structure is formed by first fabricating fins over a semiconductor substrate, followed by a formation of a source and a drain recess. A source and a drain region may then be deposited into the source and the drain recess. The gate structure may be deposited into the region between the fins. The gate structure includes dielectric and metallic layers. In the regions between the fins, the gate structure is isolated from the source and the drain region by an insulating layer.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Shi Ning Ju, Chih-Hao Wang, Kuan-Ting Pan
  • Publication number: 20220173213
    Abstract: Semiconductor structures and method for manufacturing the same are provided. The semiconductor structure includes a substrate and a first fin structure formed over the substrate. The semiconductor structure also includes an isolation structure formed around the first fin structure and a protection layer formed on the isolation structure. The semiconductor structure also includes first nanostructures formed over the first fin structure and a gate structure surrounding the first nanostructures. In addition, a bottom surface of the gate structure and the top surface of the isolation structure are separated by the protection layer.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 2, 2022
    Inventors: Wen-Ting LAN, Guan-Lin CHEN, Shi-Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG, Ching-Wei TSAI, Kuan-Lun CHENG
  • Patent number: 11349016
    Abstract: A fin field effect transistor device structure includes a first fin structure formed over a substrate. The structure also includes a fin top layer formed over a top portion of the first fin structure. The structure also includes a first oxide layer formed across the first fin structure and the fin top layer. The structure also includes a first gate structure formed over the first oxide layer across the first fin structure.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Shi-Ning Ju, Chih-Hao Wang
  • Publication number: 20220165868
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.
    Type: Application
    Filed: February 7, 2022
    Publication date: May 26, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jia-Chuan You, Chih-Hao Wang, Shi Ning Ju, Kuo-Cheng Chiang, Li-Yang Chuang
  • Patent number: 11342325
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) including a first fin structure and a second fin structure vertically extending from a semiconductor substrate, respectively. The first fin structure laterally extends along a first direction and has a first width. The second fin structure laterally extends along the first direction and has a second width that is less than the first width. A first plurality of nanostructures directly overlies the first fin structure and is vertically spaced from the first fin structure by a non-zero distance. A gate electrode continuously laterally extends along a second direction that is substantially perpendicular to the first direction. The gate electrode directly overlies the first and second fin structures, and wraps around the nanostructures.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chao Chou, Chih-Hao Wang, Shi Ning Ju, Kuo-Cheng Chiang, Wen-Ting Lan
  • Patent number: 11328963
    Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Ting Pan, Huan-Chieh Su, Zhi-Chang Lin, Shi Ning Ju, Yi-Ruei Jhan, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11329165
    Abstract: A semiconductor device structure is provided, which includes a first fin structure over a semiconductor substrate. The first fin structure has multiple first semiconductor nanostructures suspended over the semiconductor substrate. The semiconductor device structure includes a second fin structure over the semiconductor substrate, and the second fin structure has multiple second semiconductor nanostructures suspended over the semiconductor substrate. The semiconductor device structure includes a dielectric fin between the first fin structure and the second fin structure. In addition, the semiconductor device structure includes a metal gate stack wrapping around the first fin structure, the second fin structure, and the dielectric fin. The semiconductor device structure includes a dielectric protection structure over the metal gate stack.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Huan-Chieh Su, Kuan-Ting Pan, Shi-Ning Ju, Chih-Hao Wang
  • Publication number: 20220139914
    Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes providing a workpiece including a substrate, an isolation feature over the substrate, a first fin-shaped structure protruding through the isolation feature, and a second fin-shaped structure protruding through the isolation feature, forming a dielectric fin between the first and second fin-shaped structures, and forming first and second gate structures over the first and second fin-shaped structures, respectively. The exemplary manufacturing method also includes etching the isolation feature from the backside of the workpiece to from a trench exposing the dielectric fin, etching the dielectric fin from the backside of the workpiece to form an extended trench, and depositing a seal layer over the extended trench. The seal layer caps an air gap between the first and second gate structures.
    Type: Application
    Filed: June 30, 2021
    Publication date: May 5, 2022
    Inventors: Jung-Chien Cheng, Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng
  • Publication number: 20220130958
    Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a. third section between the first section and the second section.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Inventors: GUAN-LIN CHEN, KUO-CHENG CHIANG, CHIH-HAO WANG, SHI NING JU, JUI-CHIEN HUANG
  • Publication number: 20220130955
    Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.
    Type: Application
    Filed: January 6, 2021
    Publication date: April 28, 2022
    Inventors: Eric Cheng, Shi Ning Ju, Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 11315925
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Publication number: 20220115374
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked structure and a second stacked structure extending above the isolation structure. The first stacked structure includes a plurality of first nanostructures stacked in a vertical direction, and the second stacked structure includes a plurality of second nanostructures stacked in the vertical direction. The semiconductor device structure includes a first dummy fin structure formed over the isolation structure, and the first dummy fin structure is between the first stacked structure and the second stacked structure. The semiconductor device structure also includes a first capping layer formed over the first dummy fin structure, and an interface between the first dummy fin structure and the first capping layer is lower than a top surface of a topmost first nanostructure.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng CHIANG, Shi-Ning JU, Chih-Hao WANG, Kuan-Ting PAN, Zhi-Chang LIN
  • Patent number: 11302825
    Abstract: A semiconductor device includes a substrate; a channel member above the substrate; a gate structure wrapping the channel member; a source/drain (S/D) feature abutting the channel member; and an inner spacer interposing the S/D feature and the gate structure, wherein a first sidewall of the inner spacer facing the gate structure has a curvature surface in a cross-sectional view perpendicular to a top surface of the substrate and along a lengthwise direction of the channel member.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11302580
    Abstract: According to one example, a method includes performing a Chemical Mechanical Polishing (CMP) process on a semiconductor workpiece that includes a nanosheet region, the nanosheet region having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes stopping the CMP process when the first type of semiconductor material is covered by the second type of semiconductor material, patterning the nanosheet region to form nanosheet stacks, forming an isolation structure around the nanosheet stacks, removing a top layer of the second type of semiconductor material from the nanosheet stacks, recessing the isolation structure, and forming a gate structure over the nanosheet stacks.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Ting Lan, Kuan-Ting Pan, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11302693
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan You, Shi-Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang