Patents by Inventor Shi-Wei Chang

Shi-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuits with built-in self test mechanism
    Patent number: 9728276
    Abstract: An embodiment of the invention provides an integrated circuit including a core circuit and a memory. The core circuit executes operations of the integrated circuit. The memory stores a subsystem and a repair system. When the repair system runs, the repair system detects whether there is a defect in the memory. When the repair system detects the defect, the repair system repairs the defect, and when the repair system does not detect the defect, a fake defect is injected in the memory to verify whether the repair system runs correctly.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: August 8, 2017
    Assignee: MEDIATEK INC.
    Inventors: Shi-Wei Chang, Chia-Wei Wang
  • INTEGRATED CIRCUITS WITH BUILT-IN SELF TEST MECHANISM
    Publication number: 20160093401
    Abstract: An embodiment of the invention provides an integrated circuit including a core circuit and a memory. The core circuit executes operations of the integrated circuit. The memory stores a subsystem and a repair system. When the repair system runs, the repair system detects whether there is a defect in the memory. When the repair system detects the defect, the repair system repairs the defect, and when the repair system does not detect the defect, a fake defect is injected in the memory to verify whether the repair system runs correctly.
    Type: Application
    Filed: June 25, 2015
    Publication date: March 31, 2016
    Inventors: Shi-Wei CHANG, Chia-Wei WANG
  • Memory cell array
    Patent number: 9287276
    Abstract: A semiconductor memory cell array is disclosed that includes a memory cell unit. The memory cell unit includes an active region, a first transistor, a second transistor, a gate structure, and an interconnect. The first transistor and the second transistor are formed on the active region. The gate structure is formed on the active region and between the first transistor and the second transistor. The interconnect connects the gate structure and at least one of sources of the first transistor and the second transistor to a power line.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: March 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shi-Wei Chang, Hong-Chen Cheng, Chien-Chi Tien, Li-Chun Tien, Kuo-Hua Pan, Jhon-Jhy Liaw
  • Sense amplifier
    Patent number: 8970256
    Abstract: The present disclosure relates to a differential sense amplifier comprising first and second cross-coupled inverters with first and second complimentary storage nodes. A first current control element changes a current through the first cross-coupled inverter based upon an output of a second cross-coupled inverter, and a second current control element changes a current through the second cross-coupled inverter based upon an output of the first cross-coupled inverter. Other devices and methods are also disclosed.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng Hung Lee, Hektor Huang, Chi-Kai Hsieh, Shi-Wei Chang, Hong-Chen Cheng
  • MEMORY CELL ARRAY
    Publication number: 20150021701
    Abstract: A semiconductor memory cell array is disclosed that includes a memory cell unit. The memory cell unit includes an active region, a first transistor, a second transistor, a gate structure, and an interconnect. The first transistor and the second transistor are formed on the active region. The gate structure is formed on the active region and between the first transistor and the second transistor. The interconnect connects the gate structure and at least one of sources of the first transistor and the second transistor to a power line.
    Type: Application
    Filed: July 19, 2013
    Publication date: January 22, 2015
    Inventors: Shi-Wei CHANG, Hong-Chen CHENG, Chien-Chi TIEN, Li-Chun TIEN, Kuo-Hua PAN, Jhon-Jhy LIAW
  • Sense Amplifier
    Publication number: 20140266436
    Abstract: The present disclosure relates to a differential sense amplifier comprising first and second cross-coupled inverters with first and second complimentary storage nodes. A first current control element changes a current through the first cross-coupled inverter based upon an output of a second cross-coupled inverter, and a second current control element changes a current through the second cross-coupled inverter based upon an output of the first cross-coupled inverter. Other devices and methods are also disclosed.
    Type: Application
    Filed: May 7, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng Hung Lee, Hektor Huang, Chi-Kai Hsieh, Shi-Wei Chang, Hong-Chen Cheng