Patents by Inventor Shi-Wen TAN
Shi-Wen TAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240104285Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin CHUANG, Shi-Wen TAN, Song LIU, Shih-Yao LIN, Wen-Yuan FANG
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Patent number: 11893334Abstract: A method is provided and includes several operations: forming a first group of macros in a first region, wherein the first group of macros are aligned with a first boundary of a channel that is coupled thereto through pins of the first group of macros; forming a second group of macros in the first region to align with a second boundary of the channel that is coupled thereto through pins of the second group of macros, wherein the first and second groups of macros are coupled to a first register; and forming a third group of macros in a second region different from the first region. A first macro and a second macro that are in the third group of macros are aligned with the first and second boundaries respectively. The third group of macros are coupled to a second register different from the first register.Type: GrantFiled: July 27, 2022Date of Patent: February 6, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin Chuang, Shi-Wen Tan, Song Liu, Shih-Yao Lin, Wen-Yuan Fang
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Patent number: 11853675Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.Type: GrantFiled: August 8, 2022Date of Patent: December 26, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin Chuang, Shi-Wen Tan, Song Liu, Shih-Yao Lin, Wen-Yuan Fang
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Publication number: 20220382950Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin CHUANG, Shi-Wen TAN, Song LIU, Shih-Yao LIN, Wen-Yuan FANG
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Publication number: 20220366118Abstract: A method is provided and includes several operations: forming a first group of macros in a first region, wherein the first group of macros are aligned with a first boundary of a channel that is coupled thereto through pins of the first group of macros; forming a second group of macros in the first region to align with a second boundary of the channel that is coupled thereto through pins of the second group of macros, wherein the first and second groups of macros are coupled to a first register; and forming a third group of macros in a second region different from the first region. A first macro and a second macro that are in the third group of macros are aligned with the first and second boundaries respectively. The third group of macros are coupled to a second register different from the first register.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin CHUANG, Shi-Wen TAN, Song LIU, Shih-Yao LIN, Wen-Yuan FANG
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Patent number: 11443096Abstract: A method is provided in the present disclosure. The method includes several operations: generating a floor plan having multiple macros for an integrated circuit; adjusting the macros according to a channel area interposed between the pins; separating the macros by a channel width of the channel area; and adjusting, in accordance with correlations between the macros and multiple registers, the macros in the floor plan.Type: GrantFiled: October 15, 2020Date of Patent: September 13, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin Chuang, Shi-Wen Tan, Song Liu, Shih-Yao Lin, Wen-Yuan Fang
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Publication number: 20220092248Abstract: A method is provided in the present disclosure. The method includes several operations: generating a floor plan having multiple macros for an integrated circuit; adjusting the macros according to a channel area interposed between the pins; separating the macros by a channel width of the channel area; and adjusting, in accordance with correlations between the macros and multiple registers, the macros in the floor plan.Type: ApplicationFiled: October 15, 2020Publication date: March 24, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin CHUANG, Shi-Wen TAN, Song LIU, Shih-Yao LIN, Wen-Yuan FANG
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Patent number: 11263375Abstract: A method, for determining constraints related to a target circuit, includes following operations. First circuit speed results of the target circuit under different candidate constraint configurations are accumulated. Breakthrough probability distributions relative to each of the candidate constraint configurations are determined according to the first circuit speed results. First selected constraint configurations are determined from the candidate constraint configurations by sampling the breakthrough probability distributions. A first budget distribution is determined among the first selected constraint configurations. In response to that the first budget distribution is converged, the first selected constraint configurations in the first budget distribution is utilized for implementing the target circuit and generating an updated circuit speed result of the target circuit.Type: GrantFiled: June 30, 2020Date of Patent: March 1, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin Chuang, Shi-Wen Tan, Szu-Ju Huang, Shih-Feng Hong
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Publication number: 20210365620Abstract: A method, for determining constraints related to a target circuit, includes following operations. First circuit speed results of the target circuit under different candidate constraint configurations are accumulated. Breakthrough probability distributions relative to each of the candidate constraint configurations are determined according to the first circuit speed results. First selected constraint configurations are determined from the candidate constraint configurations by sampling the breakthrough probability distributions. A first budget distribution is determined among the first selected constraint configurations. In response to that the first budget distribution is converged, the first selected constraint configurations in the first budget distribution is utilized for implementing the target circuit and generating an updated circuit speed result of the target circuit.Type: ApplicationFiled: June 30, 2020Publication date: November 25, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin CHUANG, Shi-Wen TAN, Szu-Ju HUANG, Shih-Feng HONG