Abstract: A data sharing method that implements data tag to improve data sharing on a multi-computing-unit platform, wherein the multi-computing unit platform includes multiple cores, and multiple threads generating multiple critical sections on each core. When a first thread enters a first critical section to access a shared data, the shared data is temporarily stored in a first core, when the first thread leaves the first critical section, it transfers the control of the shared data to a second core that has higher transmission advantage.

Abstract: The present invention discloses a method of using memory allocation to address hot and cold data, which comprises steps: using a hardware performance monitor (HPM) to detect at least one read/write event of a central processor; while a number of the read/write events reaches a threshold or a random value, a computer system recording an access type of the read/write event occurring latest and a memory address causing the read/write event; and the computer system assigning the memory object in the memory address to a volatile memory or a non-volatile memory according to the memory address and the access type. Thereby, data pages can be assigned automatically according to the access types categorized by the central processor, exempted from being assigned manually by engineers.

Abstract: The present invention discloses a method of using memory allocation to address hot and cold data, which comprises steps: using a hardware performance monitor (HPM) to detect at least one read/write event of a central processor; while a number of the read/write events reaches a threshold or a random value, a computer system recording an access type of the read/write event occurring latest and a memory address causing the read/write event; and the computer system assigning the memory object in the memory address to a volatile memory or a non-volatile memory according to the memory address and the access type. Thereby, data pages can be assigned automatically according to the access types categorized by the central processor, exempted from being assigned manually by engineers.

Abstract: Provided is a method for fast booting/shutting down a computing system. The method includes the steps of: when the computing system enters the hibernation mode, sorting the memory of the computing system into swappable pages and non-swappable pages and writing the non-swappable pages into a hibernation file of a storage device; determining whether the swappable pages are frequently-used pages or infrequently-used pages, and if the swappable pages are determined to be frequently-used pages, incorporating the frequently-used pages in the hibernation file; sorting the infrequently-used pages into clean pages and dirty pages; capturing one of the dirty pages and adding pages that are related to the captured page into at least one data set and placing the data set into a swap space of the storage device by continuous accessing process.

Abstract: A method for initializing a peripheral device and an electronic device using the method. The electronic device includes one or more peripheral devices having registers, a memory having a data storing module, and an instruction capturing module. The instruction capturing module captures a plurality of hardware register settings from a driver execution process of the one or more peripheral devices, stores the plurality of hardware register settings in the data storing module, and serializes or concatenates the plurality of hardware register settings to form serialized hardware register settings, when the electronic device is performing a non-hibernation resume or non-wakeup cold boot to execute an initialization process of the one or more peripheral devices. The one or more peripheral devices are initialized by the serialized hardware register settings, when the electronic device is performing cold boot again due to a hibernation resume or wakeup to execute the initialization process.

Abstract: A fast speed computer system power-on & power-off method, that is used to reduce an amount of main memory transferred and stored from a main memory into a second storage device, thus speeding up a speed of re-activation of a computer system from a hibernation state into a full speed operation state. Said fast speed computer system power-on & power-off method is applicable to various types of computer systems, and can be used to write in and load back data in cooperation with a random access processing technology. In addition, said method can be used to reduce extent of data loss and damage of said computer system due to a sudden power outage of said computer system.

Abstract: A method for hibernation mechanism and a computer system therefor are provided. The method includes the followings. An initial process of a hibernation mechanism is performed in a computer system, in which a non-swappable memory of a main memory is partitioned into a plurality of non-swappable segments, and each segment corresponds to a status value indicating whether the content of the segment has been changed. During a process of entering a hibernation state, for each non-swappable segment, it is determined whether the segment is to be written to a storage device according to the status value. The segment is written into the storage device when a determination result indicates the segment has been changed, or else the computer does not write the segment to the storage device when the determination result indicates the segment is has not been changed.

Abstract: A method of a fast system call is provided. First, a logical operation to compute a kernel service routine is used. Then the logical operation result is compared with ciphertext from a key register. At least one input for the logical operation is from the relevant information of the required kernel service routine. For example, the start address of the kernel service routine or the content of the start address of the kernel service routine, or combinations thereof. If the logical operation result equals to the ciphertext of the key register, a switch from a user mode to a kernel mode to read the kernel service routine is allowed. Otherwise, the central processing system executes a corresponding exceptional handler routine. Then the operating system terminates the mode switch request and reports an error to the operating system.

Abstract: A method of accurately simulating a target machine on a simulator, wherein, a mapping table is set up in a main program to record correspondence relations between target machine instructions and host machine instructions, and a signal handler is registered in a host machine for calling said mapping table. When an interrupt occurs while said simulator is performing simulation for a target program on the host machine, signal handler searches the mapping table to obtain or dynamically calculates to obtain host machine instruction corresponding to the next target machine instruction to be executed in target program; and replacing said host machine instruction with a return instruction, thus when executing said return instruction, the simulator will return to main program in checking said interrupt and proceeding with necessary proceedings required. Through the present invention, when said interrupt occurs, said simulator may return to main program in time for handling the interrupt.

Abstract: A fast speed computer system power-on & power-off method, that is used to reduce an amount of main memory transferred and stored from a main memory into a second storage device, thus speeding up a speed of re-activation of a computer system from a hibernation state into a full speed operation state. Said fast speed computer system power-on & power-off method is applicable to various types of computer systems, and can be used to write in and load back data in cooperation with a random access processing technology. In addition, said method can be used to reduce extent of data loss and damage of said computer system due to a sudden power outage of said computer system.

Abstract: An image compression system in coordination with camera motion includes a camera for capturing motion pictures; a motion detection device structurally connected with the camera for detecting motions of the camera; an image compression electrically connected with the camera for compressing the motion pictures; and a motion vector receiver electrically connected with the motion diction device and the image compression device for receiving motion signals generated by the motions and then transmitting the motion signals to the image compression device, whereby the image compression device can refer to the motion signals for calculation while compressing the motion pictures. Accordingly, the image compression system can compress the images in coordination with the camera motion and meanwhile eliminate the minor vibrations in the images.

Abstract: A method of accessing cache memory for parallel processing processors includes providing a processor and a lower level memory unit. The processor utilizes multiple instruction processing members and multiple sub-cache memories corresponding to the instruction processing members. Next step is using a first instruction processing member to access a first sub-cache memory. The first instruction processing member will access the rest sub-cache memories when the first instruction processing member does not access the desired data successfully in the first instruction processing member. The first instruction processing member will access the lower level memory unit until the desired data have been accessed, when the first instruction processing member does not access the desired data successfully in the sub-memories. Then, the instruction processing member returns a result.

Abstract: A method of accessing cache memory for parallel processing processors includes providing a processor and a lower level memory unit. The processor utilizes multiple instruction processing members and multiple sub-cache memories corresponding to the instruction processing members. Next step is using a first instruction processing member to access a first sub-cache memory. The first instruction processing member will access the rest sub-cache memories when the first instruction processing member does not access the desired data successfully in the first instruction processing member. The first instruction processing member will access the lower level memory unit until the desired data have been accessed, when the first instruction processing member does not access the desired data successfully in the sub-memories. Then, the instruction processing member returns a result.

Abstract: A method of a fast system call is provided. First, a logical operation to compute a kernel service routine is used. Then the logical operation result is compared with ciphertext from a key register. At least one input for the logical operation is from the relevant information of the required kernel service routine. For example, the start address of the kernel service routine or the content of the start address of the kernel service routine, or combinations thereof. If the logical operation result equals to the ciphertext of the key register, a switch from a user mode to a kernel mode to read the kernel service routine is allowed. Otherwise, the central processing system executes a corresponding exceptional handler routine. Then the operating system terminates the mode switch request and reports an error to the operating system.

Abstract: An universal BSP tool for porting on embedded systems and an application method thereof are proposed. The universal BSP tool comprises a BSP parser and a code generator, and is used to parse an open reusable document in XML format, BSPXML. Hardware specification of a target embedded platform and booting process of a specific OS or application are described in the BSPXML document. After parsing of the BSPXML document, bootstrap code of a specific embedded OS or application on the target platform can be generated. BSP low-level functions are also provided by the BSP tool for further use in OS and application after booting to control the embedded hardware. The BSP tool can simplify and automate the process of porting to achieve the objective of reducing the time to market for embedded systems.