Abstract: The present application relates to the technical field of display, and discloses an OLED display panel and a display device. The OLED display panel includes a drive backplane; and an OLED device, an encapsulation structure and a color resistor structure which are arranged on the drive backplane; the encapsulation structure and the color resistor structure are located on a side, facing away from the drive backplane, of the OLED device, and the color resistor structure includes a chromatic color resistor layer, a first BM and a second BM; and the first BM is located on a side, facing away from the drive backplane, of the chromatic color resistor layer, and the second BM is located on a side, facing the drive backplane, of the chromatic color resistor layer.

Abstract: The present application relates to the technical field of display, and discloses an OLED display panel and a display device. The OLED display panel includes a drive backplane; and an OLED device, an encapsulation structure and a color resistor structure which are arranged on the drive backplane; the encapsulation structure and the color resistor structure are located on a side, facing away from the drive backplane, of the OLED device, and the color resistor structure includes a chromatic color resistor layer, a first BM and a second BM; and the first BM is located on a side, facing away from the drive backplane, of the chromatic color resistor layer, and the second BM is located on a side, facing the drive backplane, of the chromatic color resistor layer.

Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.

Abstract: A method performed by a slave device to obtain a host memory address includes: inquiring a description list to obtain information of an allocated memory of a host; dividing the allocated memory into N storage spaces according to the information; using a first memory space of the N storage spaces to store a first level look-up table indicating physical addresses of the N storage spaces; dividing the first memory space into M storage spaces; storing a second level look-up table in the slave device to indicate physical addresses of the M storage spaces; inquiring the second level look-up table according to a logical address and obtaining a first index indicating a physical address of one of the M storage spaces; and inquiring the first level look-up table according to the first index and obtaining a second index indicating a physical address of one of the N storage spaces.

Abstract: Disclosed is a reference clock gating circuit for outputting a reliable reference clock according to an external clock. The circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter counting according to triggers of the external clock and thereby generating a first clock number; a second counter counting according to triggers of an accurate slow clock and thereby generating a second clock number; and a decision circuit determining whether a ratio of the first clock number to the second clock number satisfies a predetermined condition after the second clock number reaches a predetermined number, and thereby generating a gating signal to control the gating component. If the ratio satisfies the predetermined condition, the gating component receives the external clock and outputs it as the reference clock; and if the ratio doesn't satisfy the predetermined condition, the gating component doesn't output the external clock.

Abstract: A method for exchanging messages is performed by a slave device, and includes: receiving a submission queue (SQ) tail doorbell from a host to learn that X SQ entries need to be processed, wherein “X” doesn't exceed a host SQ entry upper limit; performing multiple read operations according to the SQ tail doorbell to read the X SQ entries from the host, wherein the slave device reads Y SQ entries at most in each read operation, and “Y” is smaller than “X” and doesn't exceed a slave device SQ entry upper limit; preparing P completion queue (CQ) entries; performing multiple write operations to transmit the P CQ entries to the host, wherein the slave device transmits Q CQ entries at most in each write operation, and “Q” is smaller than “P” and doesn't exceed a slave device CQ entry upper limit; and transmitting a CQ tail doorbell to the host.

Abstract: Disclosed is a reference clock gating circuit for outputting a reliable reference clock according to an external clock. The circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter counting according to triggers of the external clock and thereby generating a first clock number; a second counter counting according to triggers of an accurate slow clock and thereby generating a second clock number; and a decision circuit determining whether a ratio of the first clock number to the second clock number satisfies a predetermined condition after the second clock number reaches a predetermined number, and thereby generating a gating signal to control the gating component. If the ratio satisfies the predetermined condition, the gating component receives the external clock and outputs it as the reference clock; and if the ratio doesn't satisfy the predetermined condition, the gating component doesn't output the external clock.

Abstract: A method performed by a slave device to obtain a host memory address includes: inquiring a description list to obtain information of an allocated memory of a host; dividing the allocated memory into N storage spaces according to the information; using a first memory space of the N storage spaces to store a first level look-up table indicating physical addresses of the N storage spaces; dividing the first memory space into M storage spaces; storing a second level look-up table in the slave device to indicate physical addresses of the M storage spaces; inquiring the second level look-up table according to a logical address and obtaining a first index indicating a physical address of one of the M storage spaces; and inquiring the first level look-up table according to the first index and obtaining a second index indicating a physical address of one of the N storage spaces.

Abstract: A method is provided. The method includes: obtaining a picture to be processed, where the picture to be processed includes a plurality of pixels, and the plurality of pixels comprise first pixels for forming an image and second pixels for forming an image background; rotating the picture to be processed, where for each rotation angle, an intermediate picture is obtained; selecting at least two pictures from the picture to be processed and several intermediate pictures for calculating an area of a bounding box surrounding the image respectively; and removing second pixels outside the bounding box in a picture with the smallest area of bounding box to obtain a processed picture.

Abstract: Test structures, methods of manufacturing thereof, and testing methods for semiconductors are disclosed. In one embodiment, a test structure for semiconductor devices includes a printed circuit board (PCB), a probe region, and a compliance mechanism disposed between the PCB and the probe region. A plurality of wires is coupled between the PCB and the probe region. End portions of the plurality of wires proximate the probe region are an integral part of the probe region.

Abstract: A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining.

Abstract: A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining.

Abstract: A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining.

Abstract: Disclosed are various embodiments for managing data indexed by a search engine. A respective identifier from a set of identifiers is assigned randomly in one or more computing devices to each one of a plurality of data records. A set of search queries is provided. A first one of the search queries encompasses all of the set of identifiers. A second search index is generated from a first search index of the data records. The first search index is queried for at most a predetermined number of unmarked ones of the data records using a search query. Each one of a result set of data records that is thereby obtained is inserted into the second search index. The result set of data records is marked in the first search index.

Abstract: A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process.

Abstract: A method and system of import and export trading is provided. The system and method includes a selection module, an import duty confirmation module, a database, and a displaying module. The selection module is configured for choosing basic information of commodity from lists of property choices provided by a website and submitting the choice to a server. The import duty confirmation module is configured for confirming HS code and duty rate corresponding to the commodity according to the choice. The database is configured for storing information of commodities, HS codes and rate of import duties. The displaying module is configured for displaying commodities provided by sellers to buyers for choosing. The sellers and buyers are in different countries or regions, when a buyer chooses one commodity, the server will provide corresponding import duty to the buyer according to the quantity of commodities and the duty rate.

Abstract: Test structures, methods of manufacturing thereof, and testing methods for semiconductors are disclosed. In one embodiment, a test structure for semiconductor devices includes a printed circuit board (PCB), a probe region, and a compliance mechanism disposed between the PCB and the probe region. A plurality of wires is coupled between the PCB and the probe region. End portions of the plurality of wires proximate the probe region are an integral part of the probe region.