Abstract: A slew rate control circuit in output driver of switching circuit to prevent power ground undershoot is introduced. The gate capacitance of lower power transistor is first fast discharged to ensure the operation of the output signal. The gate capacitance of lower power transistor is then slowly discharged to limit OUT SLEW RATE. The gate capacitance of lower power transistor is further slowly discharged when the power ground level is below common ground. With above controlling, the gate voltage slew rate of lower power transistor is reduced when the lower power transistor is almost fully turned OFF. Therefore, undershoot at the power ground is avoided. Similar slew rate control circuit can also be derived in output driver of switching circuit to prevent PVCC overshoot.

Abstract: A class D amplifier with output DC offset protection is disclosed. The DC offset protection receives a PWM input signals from the outputs and investigates the PWM output signals whether there is a large DC voltage difference is being reflected on the speaker load. If so, shutdown signal SD will be sent by the DC offset protection to the PWM control logic and gate driver, thus, shutting down the output of the class D system and preventing disastrous condition from being develop across the speaker.

Abstract: A class D amplifier with output DC offset protection is disclosed. The DC offset protection receives a PWM input signals from the outputs and investigates the PWM output signals whether there is a large DC voltage difference is being reflected on the speaker load. If so, shutdown signal SD will be sent by the DC offset protection to the PWM control logic and gate driver, thus, shutting down the output of the class D system and preventing disastrous condition from being develop across the speaker.

Abstract: A slew rate control circuit in output driver of switching circuit to prevent power ground undershoot is introduced. The gate capacitance of lower power transistor is first fast discharged to ensure the operation of the output signal. The gate capacitance of lower power transistor is then slowly discharged to limit OUT SLEW RATE. The gate capacitance of lower power transistor is further slowly discharged when the power ground level is below common ground. With above controlling, the gate voltage slew rate of lower power transistor is reduced when the lower power transistor is almost fully turned OFF. Therefore, undershoot at the power ground is avoided. Similar slew rate control circuit can also be derived in output driver of switching circuit to prevent PVCC overshoot.

Abstract: A smart protection circuit to prevent possible circuit malfunction or damage due to sudden power source voltage fluctuation is introduced. In case of quick and large voltage fluctuation in power supply, a control signal is activated to stop power transistor switching. When power supply is stable at a lower or higher operating voltage, the switching circuit is able to return to normal operation.

Abstract: A differential input Class D audio power amplifier incorporating a differential error amplifier is introduced. In response of differential input signal, this differential error amplifier generates two error signals, which subsequently generates final output signal. This architecture makes it the effect of feedback signal error correction doubled, which helps in achieving good THD. In addition, input port of this architecture is also compatible with single-ended signal. A pop noise suppression technique for this differential input Class D audio power amplifier is also introduced.

Abstract: An amplifier circuit that uses multiple power supplies includes a class D amplifier circuit, input bias generator and feedback network. By creating a voltage using the input bias generator at the non inverting terminal of the integrator, the inverting terminal of the integrator will follow the same voltage as the non inverting terminal. The offset voltage between the input signal DC bias and the input DC bias of the integrator will create an offset current flowing through the feedback resistors, thus resulting in the desired output DC bias.

Abstract: A smart protection circuit to prevent possible circuit malfunction or damage due to sudden power source voltage fluctuation is introduced. In case of quick and large voltage fluctuation in power supply, a control signal is activated to stop power transistor switching. When power supply is stable at a lower or higher operating voltage, the switching circuit is able to return to normal operation.

Abstract: An amplifier circuit that uses multiple power supplies includes a class D amplifier circuit, input bias generator and feedback network. By creating a voltage using the input bias generator at the non inverting terminal of the integrator, the inverting terminal of the integrator will follow the same voltage as the non inverting terminal. The offset voltage between the input signal DC bias and the input DC bias of the integrator will create an offset current flowing through the feedback resistors, thus resulting in the desired output DC bias.

Abstract: A differential input Class D audio power amplifier incorporating a differential error amplifier is introduced. In response of differential input signal, this differential error amplifier generates two error signals, which subsequently generates final output signal. This architecture makes it the effect of feedback signal error correction doubled, which helps in achieving good THD. In addition, input port of this architecture is also compatible with single-ended signal. A pop noise suppression technique for this differential input Class D audio power amplifier is also introduced.

Abstract: A smart overcurrent protection circuit is introduced. In case of successive current due to certain malfunctions flows in power transistor of a switching circuit a control signal is activated to stop power transistor switching. When overcurrent condition is no longer satisfied, the switching circuit is still able to return to normal operation.

Abstract: A method of controlling the charge of the bootstrap capacitor during light load or no load conditions for a non-synchronous type of DC-DC converter consists of bootstrap capacitor voltage detector, light load detector and secondary switch controller. By turning on the secondary switch during the off-time of the power transistor when the bootstrap voltage is lower than the required value under light load condition, the bootstrap capacitor voltage will be able to charge back to the required value, yet minimizing the minimum current requirement for the DC-DC converter.

Abstract: A voltage level detector (8) which activates itself by monitoring the voltage level (VSTB) at a standby pin (5) during power-up of an audio power amplifier (10), and can detect fault conditions of an output block (2), such as a short to ground at an output terminal (3), in contrast to conventional protection circuits that can operate only after power-up.

Abstract: A voltage level detector (8) activates itself through monitoring the voltage level (VSTB) at a standby pin (5) during power-up of an audio power amplifier (10), and can detect fault conditions of an output block (2). Upon detection of the (VSTB) reaching a first threshold level (Vth1) and a short to ground at the output terminal (3), the second short-to-ground detection block (81) activates a the second cutoff signal generating block (83). The recovery block (82) monitors the voltage level (VSTB) at the standby pin (5) during power-up. Upon detection of the voltage level (VSTB) reaching a second threshold level (Vth2>Vth1), the recovery block (82) deactivates the cutoff signal generating block (83). The cutoff signal generating block (83) sends a cutoff signal (Sc) to a protection switch block (71) as a request for turn-off of protection switches (7A) on activation, and on the other hand, terminal the sending of the cutoff signal (Sc) on deactivation.