Patents by Inventor Shian-Jiun Fu

Shian-Jiun Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD AND APPARATUS FOR FACILITATING COMMUNICATION BETWEEN PROGRAMMABLE LOGIC CIRCUIT AND APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH CLOCK ADJUSTMENT
    Publication number: 20180062654
    Abstract: A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.
    Type: Application
    Filed: February 2, 2015
    Publication date: March 1, 2018
    Applicant: Agate Logic Inc.
    Inventors: Kai Keung Chan, David Tsang, Shian-Jiun Fu, Chao-Chiang Chen
  • METHOD AND APPARATUS FOR FACILITATING COMMUNICATION BETWEEN PROGRAMMABLE LOGIC CIRCUIT AND APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH CLOCK ADJUSTMENT
    Publication number: 20160226491
    Abstract: A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.
    Type: Application
    Filed: February 2, 2015
    Publication date: August 4, 2016
    Applicant: Agate Logic Inc.
    Inventors: Kai Keung Chan, David Tsang, Shian-Jiun Fu, Chao-Chiang Chen
  • Method and apparatus for facilitating communication between programmable logic circuit and application specific integrated circuit with clock adjustment
    Patent number: 8981813
    Abstract: A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: March 17, 2015
    Assignee: Agate Logic, Inc.
    Inventors: Kai Keung Chan, David Tsang, Shian-Jiun Fu, Chao-Chiang Chen
  • Method and software for predicting the timing delay of a circuit path using two different timing models
    Patent number: 7484193
    Abstract: The timing response of a circuit path is predicted by modeling the circuit path using two different timing models. The variation between the timing responses produced by each of the timing models is used to generate a correction factor, which is then applied to one of the timing models. Once the correction factor has been applied to a timing model, the model is used to produce a corrected timing prediction for the modeled circuit path.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: January 27, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Aveek Sarkar, Shian-Jiun Fu, Peter Lai, Rambabu Pyapali
  • Method and software for improved circuit path timing predictions, and circuit design produced therewith
    Publication number: 20050050405
    Abstract: The timing response of a circuit path is predicted by modeling the circuit path using two different timing models (110, 120). The variation between the timing responses produced by each of the timing models is used to generate a correction factor (180), which is then applied to one of the timing models. Once the correction factor has been applied to a timing model, the model is used to produce a corrected timing prediction for the modeled circuit path.
    Type: Application
    Filed: August 28, 2003
    Publication date: March 3, 2005
    Inventors: Aveek Sarkar, Shian-Jiun Fu, Peter Lai, Rambabu Pyapali