Abstract: The present invention comprises a binary select adder for adding two numbers of N binary bits. where N=2.sup.K +R and K is an integer whereas R is an integer remainder and 0.ltoreq.R<(2.sup.K+1 -2.sup.K). The binary carry select adder comprises a plurality of full adder pairs for adding one bit of the two numbers wherein each of the pairs including a first adder for processing an initial sum and carry assuming a carry select of zero and a second adder for processing an initial sum and carry assuming a carry select of one. The binary carry select adder further includes a plurality of fourplex processing means each connected to the pair of full adders or another one of the fourplex processing means forming a plurality of intermediate stages for receiving four input data and generating a pair of appropriate intermediate `carrys`.