Patents by Inventor Shiang-Jhy Lai

Shiang-Jhy Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Zero-flag generator for adder
    Patent number: 5581496
    Abstract: Parallel processing architecture is used for an adder and its "look-ahead" zero-flag generator, which generates a flag signal for the most significant bit of the sum of the adder. The look-ahead zero-flag is generated with combinatorial logic circuits, which are fed from the addends and augents of the different bits for the adder and then decoded. The combinatorial logic circuits may comprise AND gates and XOR gates in a gate-array, and the decoder may be a programmable logic array (PLA). The computation time for the zero-flag thus generated is shorter than the computation time for the sum of the adder.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: December 3, 1996
    Assignee: Industrial Technology Research Institute
    Inventors: Shiang-Jhy Lai, Hwai-Tsu Chang