Patents by Inventor Shiao-Chian YEH

Shiao-Chian YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11211323
    Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Shiao-Chian Yeh, Hong-Jang Wu, Kuei-Shun Chen
  • Publication number: 20190252308
    Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventors: Chia-Chu Liu, Shiao-Chian Yeh, Hong-Jang Wu, Kuei-Shun Chen
  • Patent number: 10276488
    Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chu Liu, Shiao-Chian Yeh, Hong-Jang Wu, Kuei-Shun Chen
  • Publication number: 20180025968
    Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.
    Type: Application
    Filed: September 29, 2017
    Publication date: January 25, 2018
    Inventors: Chia-Chu LIU, Shiao-Chian YEH, Hong-Jang WU, Kuei-Shun CHEN
  • Patent number: 9466528
    Abstract: A method of making a structure includes forming a first supporting member over a substrate, the first supporting member comprising a first material and having a first width defined along a reference plane. The method further includes forming a second supporting member over the substrate, the second supporting member having a second width defined along the reference plane, and the first supporting member and the second supporting member being separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region being from 5 to 30 times the second width.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: October 11, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chu Liu, Yi-Shien Mor, Kuei-Shun Chen, Yu Lun Liu, Han-Hsun Chang, Shiao-Chian Yeh
  • Publication number: 20150037976
    Abstract: A method of making a structure includes forming a first supporting member over a substrate, the first supporting member comprising a first material and having a first width defined along a reference plane. The method further includes forming a second supporting member over the substrate, the second supporting member having a second width defined along the reference plane, and the first supporting member and the second supporting member being separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region being from 5 to 30 times the second width.
    Type: Application
    Filed: October 6, 2014
    Publication date: February 5, 2015
    Inventors: Chia-Chu LIU, Yi-Shien MOR, Kuei-Shun CHEN, Yu Lun LIU, Han-Hsun CHANG, Shiao-Chian YEH
  • Patent number: 8872339
    Abstract: A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Yi-Shien Mor, Kuei Shun Chen, Yu Lun Liu, Han-Hsun Chang, Shiao-Chian Yeh
  • Publication number: 20130320451
    Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.
    Type: Application
    Filed: June 1, 2012
    Publication date: December 5, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventors: Chia-Chu Liu, Shiao-Chian Yeh, Hong-Jang Wu, Kuei-Shun Chen
  • Publication number: 20130207265
    Abstract: A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.
    Type: Application
    Filed: February 10, 2012
    Publication date: August 15, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chu LIU, Yi-Shien MOR, Kuei-Shun CHEN, Yu Lun LIU, Han-Hsun CHANG, Shiao-Chian YEH