Abstract: An ESD protection design using a gate-coupled substrate-triggered technique is provided. A required RC time constant maintained in the gate-coupled substrate-triggered ESD circuit is based on a parasitic MOS capacitor and larger resistor, in which a layout area for the substrate-triggered ESD protection design is significantly reduced.

Abstract: An electrostatic discharge (ESD) protection circuit including a detection circuit for detecting an ESD current and a bypass circuit for bypassing the ESD current is provided. The detection circuit and the bypass circuit are coupled between a first pad and a second pad. The bypass circuit comprises a transistor, a diode, and a resistor. The drain of the transistor is coupled to the first pad. The source of the transistor is coupled to the second pad and a cathode of the diode. The substrate terminal of the transistor is coupled to an anode of the diode and an output terminal of the detection circuit. The resistor is coupled between the substrate terminal and the second pad. The diode keeps the voltage of the substrate terminal sufficient for turning on the transistor.

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor substrate.

Abstract: An electrostatic discharge (ESD) protection circuit including a detection circuit for detecting the ESD current and a clamp circuit for bypassing an ESD current between a first pad and a second pad is provided. The detection circuit is connected between the first pad and the second pad, wherein the detection circuit comprises a diode and a variable resistor tuned by a diode, and an output terminal of the detection circuit is connected to the variable resistor. The clamp circuit is connected between the first pad and the second pad and connected to the output terminal of the detection circuit. When the ESD current from the first pad or the second pad is detected by the detection circuit, a trigger voltage is generated to trigger the clamp circuit to bypass the ESD current due to a resistance of the variable resistor is changed by the diode.

Abstract: An electrostatic discharge (ESD) protection circuit including a detection circuit for detecting the ESD current and a clamp circuit for bypassing an ESD current between a first pad and a second pad is provided. The detection circuit is connected between the first pad and the second pad, wherein the detection circuit comprises a diode and a variable resistor tuned by a diode, and an output terminal of the detection circuit is connected to the variable resistor. The clamp circuit is connected between the first pad and the second pad and connected to the output terminal of the detection circuit. When the ESD current from the first pad or the second pad is detected by the detection circuit, a trigger voltage is generated to trigger the clamp circuit to bypass the ESD current due to a resistance of the variable resistor is changed by the diode.

Abstract: A seal-ring structure is formed on a p-substrate that is coupled to a first voltage terminal. The seal-ring structure includes an n-well, a first metal layer, a second metal layer, a first capacitor, a poly-silicon layer, and a second capacitor. The n-well is formed on the p-substrate and coupled to a second voltage terminal. The first metal layer is sited on a first dielectric layer on the p-substrate and connected to the p-substrate through a plurality of contacts. The second metal layer is sited on a second dielectric layer on the first metal layer and connected to the n-well through a plurality of contacts. The first capacitor is formed between the first metal layer and the second metal layer. The poly-silicon layer is formed between the first metal layer and the n-well. The second capacitor is formed between the poly-silicon layer and the n-well.

Abstract: A structure of an electrostatic discharge protection circuit, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.

Abstract: MOS Transistors and bipolar junction transistors are connected to input pads and output pads for implementing electrostatic discharge protection. By conducting a power clamp circuit and applying a substrate-trigger technology, electrostatic discharge protection is further enhanced. For instance, positive ESD stress protection can be enhanced between signal pads (input pads and output pads) and VSS by using NMOS transistors and field oxide devices. Negative ESD stress protection can be enhanced between signal pads and VDD by using PMOS transistors.

Abstract: An electrostatic discharge protection device, including a silicon-control-rectifier, in complementary metal-oxide semiconductor (CMOS) process is disclosed. in one embodiment of the present invention, the protection device includes a semiconductor substrate having a first conductivity type. A well region formed with a second conductivity type in the semiconductor substrate. A first region formed in the well region. A second region formed having a portion in the weil region and another portion outside the well region, but still within the semiconductor substrate. Moreover, a third region formed within the well region and in between the first; region and the second region. A fourth region formed within the semiconductor substrate and outside the well region. A fifth region formed within the semiconductor substrate and in between the second region and the fourth region.

Abstract: An ESD protection design using a gate-coupled substrate-triggered technique is provided. A required RC time constant maintained in the gate-coupled substrate-triggered ESD circuit is based on a parasitic MOS capacitor and larger resistor, in which a layout area for the substrate-triggered ESD protection design is significantly reduced.

Abstract: A semiconductor device with substrate-triggered ESD protection has a guard ring, a first MOS transistor array, a second MOS transistor array, a substrate-triggered portion, and an N-well. The first MOS transistor array, the second MOS transistor array, the substrate-triggered portion, and the N-well are formed in a region surrounded by the guard ring, and the substrate-triggered portion is located between the first MOS transistor array and the second MOS transistor array. When the ESD event occurs, the N-well is biased for directing a trigger current.

Abstract: An electrostatic discharge (ESD) protection circuit including a detection circuit for detecting an ESD current and a bypass circuit for bypassing the ESD current is provided. The detection circuit and the bypass circuit are coupled between a first pad and a second pad. The bypass circuit comprises a transistor, a diode, and a resistor. The drain of the transistor is coupled to the first pad. The source of the transistor is coupled to the second pad and a cathode of the diode. The substrate terminal of the transistor is coupled to an anode of the diode and an output terminal of the detection circuit. The resistor is coupled between the substrate terminal and the second pad. The diode keeps the voltage of the substrate terminal sufficient for turning on the transistor.

Abstract: An electrostatic discharge (ESD) protection circuit formed on a P-type substrate has a first p+ diffusion region in the P-type substrate, a N-well in the P-type substrate, a first n+ diffusion region in the N-well, a P-well in the N-well, and an n-p-n bipolar junction transistor (BJT) in the P-well. An equivalent circuit between a base and an emitter of the BJT is a diode without connecting to any resistor in parallel.

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor substrate.

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

Abstract: A BiCMOS electrostatic discharge (ESD) protecting circuit is triggered by a bipolar junction transistor (BJT) for achieving ESD protection. Due to the layout area of the BJT ESD protecting circuit being smaller than the layout area of an RC circuit, layout area can be reduced. Moreover, the BJT reduces leakage current problems and has a lower triggering voltage. Therefore, the BJT in the ESD protecting circuit can effectively reduce problems of a higher triggering ESD voltage and leakage current.

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

Abstract: A semiconductor device with substrate-triggered ESD protection has a guard ring, a first MOS transistor array, a second MOS transistor array, a substrate-triggered portion, and an N-well. The first MOS transistor array, the second MOS transistor array, the substrate-triggered portion, and the N-well are formed in a region surrounded by the guard ring, and the substrate-triggered portion is located between the first MOS transistor array and the second MOS transistor array. When the ESD event occurs, the N-well is biased for directing a trigger current.

Abstract: An electrostatic discharge (ESD) protection circuit formed on a P-type substrate has a first p+ diffusion region in the P-type substrate, a N-well in the P-type substrate, a first n+ diffusion region in the N-well, a P-well in the N-well, and an n-p-n bipolar junction transistor (BJT) in the P-well. An equivalent circuit between a base and an emitter of the BJT is a diode without connecting to any resistor in parallel.

Abstract: An electrostatic discharge (ESD) protection device including an ESD protection circuit is provided. The ESD protection circuit includes at least a diode connected in series between a first voltage and a pad, and at least an ESD component connected in series between a second voltage and a pad. Each of the at least an ESD component comprises a deep N-well region formed in a P-type substrate, a triple P-well formed in the deep N-well region, and a highly doped N-type (N+) region and a highly doped P-type (P+) region formed in the triple P-well region.