Abstract: An electronic apparatus includes a processing unit, a buffer memory and a buffer manager. The buffer memory includes some packet buffer slots. Each of the packet buffer slots aligns to a packet size. The buffer manager includes a cache for registering available pointers. Each of the available pointers is configured to mark a start address of one of the packet buffer slots. The buffer manager is configured to monitor an available pointer count of the available pointers. When the processing unit transmits an allocation request to the buffer manager and the available count is enough, the buffer manager obtains one available pointer from the cache and integrates the one available pointer and the available pointer count into an allocation response, which is sent to the processing unit.

Abstract: An all-digital phase-locked loop (ADPLL) includes: a digital phase frequency detector (PFD) for generating a detection signal by detecting frequency difference and phase difference between a reference signal and a feedback signal; a digital phase difference counter coupled to the digital PFD for sampling the detection signal according to an oscillator signal to thereby generate a count value; a digital filter coupled to the digital phase difference counter for generating a control signal according to the count value; a digital controlled oscillator (DCO) coupled to the digital filter for generating the oscillator signal according to the control signal; and a frequency divider coupled to the DCO and the digital PFD for generating the feedback signal by dividing the oscillator signal.

Abstract: An all-digital phase-locked loop (ADPLL) includes: a digital phase frequency detector (PFD) for generating a detection signal by detecting frequency difference and phase difference between a reference signal and a feedback signal; a digital phase difference counter coupled to the digital PFD for sampling the detection signal according to an oscillator signal to thereby generate a count value; a digital filter coupled to the digital phase difference counter for generating a control signal according to the count value; a digital controlled oscillator (DCO) coupled to the digital filter for generating the oscillator signal according to the control signal; and a frequency divider coupled to the DCO and the digital PFD for generating the feedback signal by dividing the oscillator signal.