Abstract: A computing-in-memory circuit comprises a computing element array and an analog-to-digital conversion circuit. The computing element array is utilized for analog computation operations. The computing element array includes memory cells, a first group of computing elements, and a second group of computing elements. The first group of computing elements provides capacitance for analog computation in response to an input vector and receives data from the plurality of memory cells and the input vector. The second group of computing elements provides capacitance for quantization. Each computing element of the computing element array is based on a switched-capacitors circuit. The analog-to-digital conversion circuit includes a comparator and a conversion control unit. The comparator has a signal terminal, a reference terminal, and a comparison output terminal, wherein the first and second groups of computing elements are selectively coupled to the signal terminal and the reference terminal.

Abstract: A computing-in-memory circuit comprises a computing element array and an analog-to-digital conversion circuit. The computing element array is utilized for analog computation operations. The computing element array includes memory cells, a first group of computing elements, and a second group of computing elements. The first group of computing elements provides capacitance for analog computation in response to an input vector and receives data from the plurality of memory cells and the input vector. The second group of computing elements provides capacitance for quantization. Each computing element of the computing element array is based on a switched-capacitors circuit. The analog-to-digital conversion circuit includes a comparator and a conversion control unit. The comparator has a signal terminal, a reference terminal, and a comparison output terminal, wherein the first and second groups of computing elements are selectively coupled to the signal terminal and the reference terminal.

Abstract: A DC offset cancellation circuit is provided. The DC offset cancellation circuit includes a first operational amplifier and a feedback gain circuit. The first operational amplifier includes a first input transconductance stage, a second input transconductance stage and an output stage. An input terminal of the first input transconductance stage receives an input signal of the first operational amplifier through a first input terminal of the first operational amplifier. An output terminal of the output stage outputs an output signal of the first operational amplifier through an output terminal of the first operational amplifier. An input terminal of the feedback gain circuit is coupled to the output terminal of the first operational amplifier, and an output terminal of the feedback gain circuit is coupled to the input terminal of the second transconductance stage through a second input terminal of the first operational amplifier.

Abstract: A DC offset cancellation circuit is provided. The DC offset cancellation circuit includes a first operational amplifier and a feedback gain circuit. The first operational amplifier includes a first input transconductance stage, a second input transconductance stage and an output stage. An input terminal of the first input transconductance stage receives an input signal of the first operational amplifier through a first input terminal of the first operational amplifier. An output terminal of the output stage outputs an output signal of the first operational amplifier through an output terminal of the first operational amplifier. An input terminal of the feedback gain circuit is coupled to the output terminal of the first operational amplifier, and an output terminal of the feedback gain circuit is coupled to the input terminal of the second transconductance stage through a second input terminal of the first operational amplifier.

Abstract: A voltage buffer having a fist transistor, a second transistor, a third transistor and a voltage detector is provided. A first terminal of the first transistor is coupled to a first reference voltage. A first terminal of the second transistor is coupled to a second terminal of the first transistor, a control terminal of the second transistor is coupled to an input voltage, and a second terminal of the second transistor is coupled to an output voltage. A first terminal of the third transistor is coupled to a second terminal of the second transistor. A second terminal of the third transistor is coupled to a second reference voltage. The voltage detector detects a voltage of the second terminal of the first transistor to generate a detection result and outputs the detection result to a bulk terminal of the second transistor.

Abstract: A resistor-capacitor (RC) calibration circuit includes: a current source, providing a current to a first node; a first switch, coupled between the first node and a second node; a second switch, coupled between the first node and a third node; a resistor, coupled between a reference terminal and the second node; a variable capacitor, coupled between the reference terminal and the third node; a third switch, coupled between the third node and the reference terminal; a comparator, comprising a first input coupled to the second node and a second input coupled to the third node; and a logic controller, coupled between an output of the comparator and the variable capacitor for outputting an adjusting signal according to an output signal of the comparator to adjust a capacitance of the variable capacitor.

Abstract: A voltage buffer having a first transistor, a second transistor, a third transistor and a voltage detector is provided. A first terminal of the first transistor is coupled to a first reference voltage. A first terminal of the second transistor is coupled to a second terminal of the first transistor, a control terminal of the second transistor is coupled to an input voltage, and a second terminal of the second transistor is coupled to an output voltage. A first terminal of the third transistor is coupled to a second terminal of the second transistor. A second terminal of the third transistor is coupled to a second reference voltage. The voltage detector detects a voltage of the second terminal of the first transistor to generate a detection result and outputs the detection result to a bulk terminal of the second transistor.

Abstract: A resistor-capacitor (RC) calibration circuit includes: a current source, providing a current to a first node; a first switch, coupled between the first node and a second node; a second switch, coupled between the first node and a third node; a resistor, coupled between a reference terminal and the second node; a variable capacitor, coupled between the reference terminal and the third node; a third switch, coupled between the third node and the reference terminal; a comparator, comprising a first input coupled to the second node and a second input coupled to the third node; and a logic controller, coupled between an output of the comparator and the variable capacitor for outputting an adjusting signal according to an output signal of the comparator to adjust a capacitance of the variable capacitor.

Abstract: A DC offset calibration apparatus including a signal processing unit, a comparison unit, a first resistor array, a second resistor array, and a resistor array control unit is provided. The signal processing unit receives an input differential signal and generates an output differential signal. The comparison unit detects and determines a first DC output voltage and a second DC output voltage of the output differential signal and generates a DC offset signal. First ends of the first resistor array and the second resistor array are respectively coupled to a first input terminal and a second input terminal of the signal processing unit. The resistor array control unit adjusts resistances of the first and the second resistor array according to the DC offset signal and a bit code sequence until the DC offset signal enters a transient state, so as to calibrate a DC offset voltage in the output differential signal.

Abstract: A low noise amplifier including an amplifier kernel circuit and a DC bias unit is provided. The amplifier kernel circuit is used for receiving a single input signal or a differential input signal so as to output a differential output signal. The DC bias unit is coupled to the amplifier kernel circuit, and is used for processing a signal source to generate the single input signal or the differential input signal according to its circuit configuration.

Abstract: A low noise amplifier including an amplifier kernel circuit and a DC bias unit is provided. The amplifier kernel circuit is used for receiving a single input signal or a differential input signal so as to output a differential output signal. The DC bias unit is coupled to the amplifier kernel circuit, and is used for processing a signal source to generate the single input signal or the differential input signal according to its circuit configuration.

Abstract: A low-noise amplifier circuit includes a MOS transistor in a common gate amplifier configuration. A single-ended input is at a source of the MOS transistor. A resonant cavity filter circuit is coupled to a gate of the MOS transistor.

Abstract: An operational amplifier includes a first stage and a second stage, the first stage for receiving two input signals and the second stage being coupled to the first stage, wherein the second stage includes a first part with a first output of the operational amplifier, and a second part with a second output of the operational amplifier. A method includes providing a first current to the first part of the second stage, and providing a second current to the second part of the second stage. The method further includes adjusting the first current based on a current consumption of the first part of the second stage, and adjusting the second current based on a current consumption of the second part of the second stage, wherein the sum of the first current and the second current is substantially constant.

Abstract: A frequency synthesizer includes: a fractional-N synthesizer configured to provide, in a locked condition, an output signal with an output frequency based on an input signal with a reference frequency, the fractional-N synthesizer including a charge pump outputting a current to be calibrated; a lock detector coupled to the fractional-N synthesizer to detect the locked condition, the lock detector being configured to send a first signal indicating the detection; a calibration component coupled to the lock detector and the fractional-N synthesizer, the calibration component being configured to provide a second signal to calibrate the current after receiving the first signal, based on a voltage sampled from the fractional-N synthesizer; and a current source array coupled to the calibration component and the fractional N synthesizer, the current source array being configured to calibrate the current based on the second signal.

Abstract: A variable gain amplifier to convert an amplifier input voltage to an amplifier output voltage, the variable gain amplifier includes: a plurality of cascode amplifiers coupled in series; a plurality of switching transistor pair circuits coupled in series; and a bias circuit coupled to provide bias voltages to each of the plurality of cascode amplifiers; wherein each of the switching transistor pair circuits is further coupled between two consecutive ones of the cascode amplifiers; a first one of the cascode amplifiers is configured to receive the amplifier input voltage; and a last one of the cascode amplifiers is configured to provide the amplifier output voltage.

Abstract: A low-noise amplifier circuit to convert a single-ended input into a dual-ended output includes an input transconductance stage circuit, including a first MOS transistor coupled in parallel with a second MOS transistor; a current buffer circuit, including a third MOS transistor coupled in parallel with a fourth MOS transistor; each of the first, second, third, and fourth transistors having a body, gate, source, and drain; the input transconductance stage circuit and the current buffer circuit being cascode coupled, forming a cascode amplifier configuration; the single-ended input being at the source of one of the first and second transistors in the input transconductance stage circuit; the dual-ended output being a differential output across the drain of the third transistor and the drain of the fourth transistor; the first and second transistors of the input transconductance stage circuit being cross-coupled, wherein the body of the first transistor is coupled to the source of the second transistor, and the

Abstract: A calibration apparatus includes an RC integrator circuit. The calibration apparatus further includes a bandwidth setting controller to provide a bandwidth setting code indicating a reference bandwidth value for calibration of the RC integrator circuit and a capacitance code generator, coupled to the RC integrator circuit, to generate a capacitance code to adjust a capacitance of the RC integrator circuit using the bandwidth setting code and a current capacitance value of the RC integrator circuit.

Abstract: A variable gain amplifier to convert an amplifier input voltage to an amplifier output voltage, the variable gain amplifier includes: a plurality of cascode amplifiers coupled in series; a plurality of switching transistor pair circuits coupled in series; and a bias circuit coupled to provide bias voltages to each of the plurality of cascode amplifiers; wherein each of the switching transistor pair circuits is further coupled between two consecutive ones of the cascode amplifiers; a first one of the cascode amplifiers is configured to receive the amplifier input voltage; and a last one of the cascode amplifiers is configured to provide the amplifier output voltage.

Abstract: A frequency synthesizer includes: a fractional-N synthesizer configured to provide, in a locked condition, an output signal with an output frequency based on an input signal with a reference frequency, the fractional-N synthesizer including a charge pump outputting a current to be calibrated; a lock detector coupled to the fractional-N synthesizer to detect the locked condition, the lock detector being configured to send a first signal indicating the detection; a calibration component coupled to the lock detector and the fractional-N synthesizer, the calibration component being configured to provide a second signal to calibrate the current after receiving the first signal, based on a voltage sampled from the fractional-N synthesizer; and a current source array coupled to the calibration component and the fractional N synthesizer, the current source array being configured to calibrate the current based on the second signal.

Abstract: A low-noise amplifier circuit to convert a single-ended input into a dual-ended output includes an input transconductance stage circuit, including a first MOS transistor coupled in parallel with a second MOS transistor; a current buffer circuit, including a third MOS transistor coupled in parallel with a fourth MOS transistor; each of the first, second, third, and fourth transistors having a body, gate, source, and drain; the input transconductance stage circuit and the current buffer circuit being cascode coupled, forming a cascode amplifier configuration; the single-ended input being at the source of one of the first and second transistors in the input transconductance stage circuit; the dual-ended output being a differential output across the drain of the third transistor and the drain of the fourth transistor; the first and second transistors of the input transconductance stage circuit being cross-coupled, wherein the body of the first transistor is coupled to the source of the second transistor, and the