Abstract: A method that determines the maximum number of logic cells that can be placed in a predetermined area on the base of an integrated circuit, and meet a voltage drop requirement. The method iteratively changes the logic cell spacing until the voltage drop requirement is made. This is done prior to the placement and extraction design phases as was done in previous methods. The predetermined area may be extrapolated across the base of the integrated circuit and meet the voltage drop requirements without the need to change the power grid, or to redo the placement and extraction phases. An integrated circuit designed according to the method, and an integrated circuit design system for using the method is also disclosed.

Abstract: A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit.

Abstract: A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit.

Abstract: A method that determines the maximum number of logic cells that can be placed in a predetermined area on the base of an integrated circuit, and meet a voltage drop requirement. The method iteratively changes the logic cell spacing until the voltage drop requirement is made. This is done prior to the placement and extraction design phases as was done in previous methods. The predetermined area may be extrapolated across the base of the integrated circuit and meet the voltage drop requirements without the need to change the power grid, or to redo the placement and extraction phases. An integrated circuit designed according to the method, and an integrated circuit design system for using the method is also disclosed.