Patents by Inventor Shich-Chang Suen
Shich-Chang Suen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230405756Abstract: Embodiments of the present disclosure relate a CMP tool and methods for planarization a substrate. Particularly, embodiments of the present disclosure provide a substrate transporter for use in a CMP tool. The transporter may be used transport and/or carry substrates among various polishers and cleaners in a CMP tool while preventing the substrates from drying out during transportation. By keeping surfaces of the substrates wet during substrate waiting time or idle time in the CMP tool, embodiments of the present disclosure prevent many types of defects, such as byproducts, agglomerated abrasives, pad debris, slurry residues, from accumulate on the substrate surface during CMP processing, thus improve yields and device performance.Type: ApplicationFiled: May 24, 2022Publication date: December 21, 2023Inventors: Te-Chien HOU, Chih Hung CHEN, Kang HUANG, Wen-Pin LIAO, Shich-Chang SUEN, Kei-Wei CHEN
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Publication number: 20230398659Abstract: Polishing pads having varying protrusions and methods of forming the same are disclosed. In an embodiment, a polishing pad includes a polishing pad substrate; a first protrusion on the polishing pad substrate, the first protrusion including a central region and a peripheral region surrounding the central region, and a first hardness of the central region being greater than a second hardness of the peripheral region; and a first groove adjacent a first side of the first protrusion.Type: ApplicationFiled: August 29, 2022Publication date: December 14, 2023Inventors: Te-Chien Hou, Chih Hung Chen, Liang-Che Chen, Shich-Chang Suen, Liang-Guang Chen
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Publication number: 20230390882Abstract: Disclosed are a chemical mechanical polishing apparatus, a control method for the chemical mechanical polishing apparatus and a chemical mechanical polishing system. In one embodiment, the chemical mechanical polishing apparatus includes a polishing pad, a sensor, a polishing head and a conditioner. The sensor is configured to obtain surface roughness of the polishing pad. The polishing head is located above the polishing pad and configured to polish a wafer which is push against the polishing pad. The conditioner is located on the polishing pad and configured to recondition the polishing pad, wherein the conditioner is operated according to at least one polishing condition, and the polishing condition is tuned according to the surface roughness of the polishing pad.Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Te-Chien Hou, Wen-Pin Liao, Chen-Chi Tang, Shich-Chang Suen, Kei-Wei Chen
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Patent number: 11728215Abstract: A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.Type: GrantFiled: May 28, 2021Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shich-Chang Suen, Kei-Wei Chen, Liang-Guang Chen
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Patent number: 11718812Abstract: A cleaning composition for cleaning a surface of a substrate comprising silicon germanium after a chemical mechanical polishing process is provided. The cleaning composition includes an oligomeric or polymeric polyamine, at least one wetting agent, a pH adjusting agent, and a solvent.Type: GrantFiled: March 3, 2021Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ji Cui, William Weilun Hong, Gin-Chen Huang, Shich-Chang Suen, Kei-Wei Chen
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Publication number: 20230021149Abstract: Some implementations described herein relate to dispensing a slurry onto a polishing pad for a chemical-mechanical planarization (CMP) process. These implementations also involve rotating the polishing pad while the slurry is dispensed onto the polishing pad. Rotation of the polishing pad results in a traversal of the slurry radially outward toward a polishing pad outer edge of the polishing pad. The polishing pad includes a plurality of groove segments and a geometric patterns formed by the plurality of the groove segments impede the flow of the slurry to the polishing pad outer edge.Type: ApplicationFiled: November 2, 2021Publication date: January 19, 2023Inventors: Te-Chien HOU, Chih Hung CHEN, Shich-Chang SUEN, Liang-Guang CHEN, Wen-Pin LIAO, Kei-Wei CHEN
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Publication number: 20220359189Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Shich-Chang Suen, Li-Chieh Wu, Chi-Jen Liu, He Hui Peng, Liang-Guang Chen, Yung-Chung Chen
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Patent number: 11410846Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.Type: GrantFiled: November 10, 2020Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shich-Chang Suen, Li-Chieh Wu, Chi-Jen Liu, He Hui Peng, Liang-Guang Chen, Yung-Chung Chen
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Publication number: 20210371774Abstract: A cleaning composition for cleaning a surface of a substrate comprising silicon germanium after a chemical mechanical polishing process is provided. The cleaning composition includes an oligomeric or polymeric polyamine, at least one wetting agent, a pH adjusting agent, and a solvent.Type: ApplicationFiled: March 3, 2021Publication date: December 2, 2021Inventors: Ji CUI, William Weilun HONG, Gin-Chen HUANG, Shich-Chang SUEN, Kei-Wei CHEN
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Publication number: 20210296173Abstract: A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.Type: ApplicationFiled: May 28, 2021Publication date: September 23, 2021Inventors: Shich-Chang Suen, Kei-Wei Chen, Liang-Guang Chen
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Patent number: 11117239Abstract: An abrasive slurry composition for chemical mechanical planarization/polishing (CMP) is provided. The abrasive slurry includes colloidal alumina, a dispersant, and a pH buffer. The colloidal alumina has a particle size of between about 5 nm and about 100 nm. The colloidal alumina may be alpha phase material having a first hardness of about 9 Mohs, or gamma phase material having a second hardness of about 8 Mohs. The abrasive slurry may further include polyacrylic acid (PAA), a down-force enhancer, or a polish-rate inhibitor.Type: GrantFiled: July 2, 2018Date of Patent: September 14, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shich-Chang Suen, Kei-Wei Chen, Liang-Guang Chen
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Publication number: 20210220962Abstract: A polishing platform of a polishing apparatus includes a platen, a polishing pad, and an electric field element disposed between the platen and the polishing pad. The polishing apparatus further includes a controller configured to apply voltages to the electric field element. A first voltage is applied to the electric field element to attract charged particles of a polishing slurry toward the polishing pad. The attracted particles reduce overall topographic variation of a polishing surface presented to a workpiece for polishing. A second voltage is applied to the electric field element to attract additional charged particles of the polishing slurry toward the polishing pad. The additional attracted particles further reduce overall topographic variation of the polishing surface presented to the workpiece. A third voltage is applied to the electric field element to repel charged particles of the polishing slurry away from the polishing pad for improved cleaning thereof.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Shich-Chang Suen, Liang-Guang Chen, Kei-Wei Chen
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Patent number: 11024540Abstract: A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.Type: GrantFiled: December 3, 2019Date of Patent: June 1, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shich-Chang Suen, Kei-Wei Chen, Liang-Guang Chen
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Patent number: 10967478Abstract: A polishing platform of a polishing apparatus includes a platen, a polishing pad, and an electric field element disposed between the platen and the polishing pad. The polishing apparatus further includes a controller configured to apply voltages to the electric field element. A first voltage is applied to the electric field element to attract charged particles of a polishing slurry toward the polishing pad. The attracted particles reduce overall topographic variation of a polishing surface presented to a workpiece for polishing. A second voltage is applied to the electric field element to attract additional charged particles of the polishing slurry toward the polishing pad. The additional attracted particles further reduce overall topographic variation of the polishing surface presented to the workpiece. A third voltage is applied to the electric field element to repel charged particles of the polishing slurry away from the polishing pad for improved cleaning thereof.Type: GrantFiled: July 10, 2018Date of Patent: April 6, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shich-Chang Suen, Liang-Guang Chen, Kei-Wei Chen
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Publication number: 20210082688Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.Type: ApplicationFiled: November 10, 2020Publication date: March 18, 2021Inventors: Shich-Chang Suen, Li-Chieh Wu, Chi-Jen Liu, He Hui Peng, Liang-Guang Chen, Yung-Chung Chen
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Patent number: 10847359Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.Type: GrantFiled: April 20, 2017Date of Patent: November 24, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shich-Chang Suen, Li-Chieh Wu, Chi-Jen Liu, He Hui Peng, Liang-Guang Chen, Yung-Chung Chen
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Patent number: 10755934Abstract: A chemical mechanical polishing (CMP) system and associated semiconductor fabrication methods are disclosed herein. An exemplary method includes performing a planarization process in a polishing unit of a CMP system to planarize a surface of a material layer using a CMP slurry. The method further includes, after performing the planarization process, performing a buffing process in the polishing unit of the CMP system to buff the surface of the material layer using an ozone gas dissolved in deionized water (O3/DIW) solution. The method further includes controlling the performing of the planarization process and the performing of the buffing process, such that the CMP slurry is received by the polishing unit from a first pipeline during the planarization process and the O3/DIW solution is received by the polishing unit from a second pipeline during the buffing process.Type: GrantFiled: December 11, 2019Date of Patent: August 25, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shich-Chang Suen, Chi-Jen Liu, Ying-Liang Chuang, Li-Chieh Wu, Liang-Guang Chen, Ming-Liang Yen
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Publication number: 20200118823Abstract: A chemical mechanical polishing (CMP) system and associated semiconductor fabrication methods are disclosed herein. An exemplary method includes performing a planarization process in a polishing unit of a CMP system to planarize a surface of a material layer using a CMP slurry. The method further includes, after performing the planarization process, performing a buffing process in the polishing unit of the CMP system to buff the surface of the material layer using an ozone gas dissolved in deionized water (O3/DIW) solution. The method further includes controlling the performing of the planarization process and the performing of the buffing process, such that the CMP slurry is received by the polishing unit from a first pipeline during the planarization process and the O3/DIW solution is received by the polishing unit from a second pipeline during the buffing process.Type: ApplicationFiled: December 11, 2019Publication date: April 16, 2020Inventors: Shich-Chang SUEN, Chi-Jen LIU, Ying-Liang CHUANG, Li-Chieh WU, Liang-Guang CHEN, Ming-Liang YEN
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Publication number: 20200105599Abstract: A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.Type: ApplicationFiled: December 3, 2019Publication date: April 2, 2020Inventors: Shich-Chang Suen, Kei-Wei Chen, Liang-Guang Chen
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Patent number: 10515808Abstract: A chemical mechanical polishing (CMP) system includes an O3/DIW generator, a polishing unit, and a cleaning unit. The O3/DIW generator is configured to generate an O3/DIW solution including ozone gas (O3) dissolved in deionized water (DIW). The polishing unit includes components for buffing a surface of a semiconductor structure, and a pipeline coupled to the O3/DIW generator to receive the O3/DIW solution for the buffing. The cleaning unit is coupled to the O3/DIW generator and is configured to clean the surface of the semiconductor structure using the O3/DIW solution.Type: GrantFiled: September 16, 2016Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shich-Chang Suen, Chi-Jen Liu, Ying-Liang Chuang, Li-Chieh Wu, Liang-Guang Chen, Ming-Liang Yen