Abstract: A polar encoder kernel, a communication unit, an integrated circuit and a method of polar encoding are described. The polar encoder kernal is configured to receive one or more bits from a kernal information block having a kernal block size of N; and output one or more bits from a kernal encoded block having a block size that matches the kernal block size N; wherein the polar encoder kernal comprises a decomposition of a polar code graph having multiple columns that are processed by a reused single datapath, at least one of said multiple columns contains two or more stages and where each column of the multiple columns is further decomposed into one or more polar code sub-graphs and is configured to process encoded bits one polar code sub-graph at a time.

Abstract: An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=?n/w?) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=?n/w?) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive t=?n/w? clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n?k bits adopt a complementary binary value.

Abstract: A polar decoder kernal is described. The polar decoder kernal includes a processing unit having: at least one input configured to receive at least one input Logarithmic Likelihood Ratio, LLR; a logic circuit configured to manipulate the at least one input LLR; and at least one output configured to output the manipulated at least one LLR. The logic circuit of the processing unit includes only a single two-input adder to manipulate the at least one input LLR, and the input LLR and manipulated LLR are in a format of a fixed-point number representation that comprises a two's complement binary number and an additional sign bit.

Abstract: A polar decoder kernal is described. The polar decoder kernal is configured to: receive one or more soft bits from a soft kernal encoded block having a block size of N and output one or more recovered kernal information bits from a recovered kernal information block having a block size of N. The polar decoder kernal comprises a decomposition of a polar code graph into an arbitrary number of columns depending on the kernal block size N.

Abstract: A polar coder circuit is described. The polar coder circuit comprises one or more datapaths; and at least one logical three-dimensional, 3D, memory block coupled to the one or more datapaths and comprising a number of one or more random access memories, RAMs, of the logical 3D memory block as a first dimension, wherein the one or more RAMs comprise(s) a width of one or more element(s) as a second dimension and a depth of one or more address(es) as a third dimension and wherein the first dimension or the second dimension has a size 2sd, where sd is a number of stages in a datapath of the one or more datapaths.

Abstract: An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=?n/w?) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=?n/w?) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive t=?n/w? clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n?k bits adopt a complementary binary value.

Abstract: An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=?n/w?) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=?n/w?) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive t=?n/w? clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n?k bits adopt a complementary binary value.

Abstract: A polar coder circuit is described. The polar coder circuit comprises one or more datapaths; and at least one logical three-dimensional, 3D, memory block coupled to the one or more datapaths and comprising a number of one or more random access memories, RAMs, of the logical 3D memory block as a first dimension, wherein the one or more RAMs comprise(s) a width of one or more element(s) as a second dimension and a depth of one or more address(es) as a third dimension and wherein the first dimension or the second dimension has a size 2sd, where sd is a number of stages in a datapath of the one or more datapaths.

Abstract: A polar decoder kernal is described. The polar decoder kernal includes a processing unit having: at least one input configured to receive at least one input Logarithmic Likelihood Ratio, LLR; a logic circuit configured to manipulate the at least one input LLR; and at least one output configured to output the manipulated at least one LLR. The logic circuit of the processing unit includes only a single two-input adder to manipulate the at least one input LLR, and the input LLR and manipulated LLR are in a format of a fixed-point number representation that comprises a two's complement binary number and an additional sign bit.

Abstract: A polar encoder kernel, a communication unit, an integrated circuit and a method of polar encoding are described. The polar encoder kernal is configured to receive one or more bits from a kernal information block having a kernal block size of N; and output one or more bits from a kernal encoded block having a block size that matches the kernal block size N; wherein the polar encoder kernal comprises a decomposition of a polar code graph having multiple columns that are processed by a reused single datapath, at least one of said multiple columns contains two or more stages and where each column of the multiple columns is further decomposed into one or more polar code sub-graphs and is configured to process encoded bits one polar code sub-graph at a time.

Abstract: A polar decoder kernal is described. The polar decoder kernal is configured to: receive one or more soft bits from a soft kernal encoded block having a block size of N and output one or more recovered kernal information bits from a recovered kernal information block having a block size of N. The polar decoder kernal comprises a decomposition of a polar code graph into an arbitrary number of columns depending on the kernal block size N.

Abstract: An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=?n/w?) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=?n/w?) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive t=?n/w? clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n?k bits adopt a complementary binary value.