Patents by Inventor Shidlingeshwar Khatakalle

Shidlingeshwar Khatakalle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111598
    Abstract: In an embodiment, a processor may include a plurality of processing engines and a sequencing circuit. The sequencing circuit may be to: detect a completed execution of a first workload by a first processing engine; in response to a detection of the completed execution of the first workload by the first processing engine, identify at least one processing engine specified as consecutive to the first processing engine in a sequence mapping; and activate the at least one processing engine specified as consecutive to execute a second workload.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Shidlingeshwar Khatakalle, Vijay Anand Mathiyalagan, Diyanesh Babu Chinnakkonda Vidyapoornachary
  • Publication number: 20230137769
    Abstract: Systems, apparatuses and methods may provide for operating system (OS) technology that determines an average bandwidth consumption with respect to a memory device, wherein the average bandwidth consumption is dedicated to a previous execution of a thread in a multi-threaded execution environment, stores the average bandwidth consumption, and sends the average bandwidth consumption to a power management unit in response to a subsequent execution of the thread being scheduled. Additionally, logic hardware technology may include a first set of registers to accumulate an average bandwidth consumption for a plurality of threads on a per thread basis with respect to the memory device, wherein the average bandwidth consumption corresponds to previous executions of the plurality of threads. The logic hardware technology determines a minimum bandwidth demand based on the average bandwidth consumption and sets a dynamic voltage and frequency scaling point based on the minimum bandwidth demand.
    Type: Application
    Filed: November 3, 2021
    Publication date: May 4, 2023
    Inventors: Vijay Anand Mathiyalagan, Stephen H. Gunther, Shidlingeshwar Khatakalle, Diyanesh Babu Chinnakkonda Vidyapoornachary
  • Patent number: 10872812
    Abstract: Various embodiments include, for example, a noise suppression filter for a power-delivery network (PDN). In one exemplary embodiment, a capacitor device, which may be used as at least a portion of the noise suppression filter, includes a first conductive plate and a second conductive plate with a dielectric material formed between the first conductive plate and the second conductive plate. A floating conductive fill layer is formed within the dielectric material and between the first conductive plate and the second conductive plate. Other embodiments of capacitors, and methods of forming the capacitor, are disclosed.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 22, 2020
    Assignee: Intel IP Corporation
    Inventors: Saravana Maruthamuthu, Shankar Chandrasekaran Jayendra, Shidlingeshwar Khatakalle
  • Publication number: 20190279899
    Abstract: Various embodiments include, for example, a noise suppression filter for a power-delivery network (PDN). In one exemplary embodiment, a capacitor device, which may be used as at least a portion of the noise suppression filter, includes a first conductive plate and a second conductive plate with a dielectric material formed between the first conductive plate and the second conductive plate. A floating conductive fill layer is formed within the dielectric material and between the first conductive plate and the second conductive plate. Other embodiments of capacitors, and methods of forming the capacitor, are disclosed.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Inventors: Saravana Maruthamuthu, Shankar Chandrasekaran Jayendra, Shidlingeshwar Khatakalle
  • Patent number: 10278025
    Abstract: The apparatus of a first wireless communication device includes memory comprising instructions and processing circuitry coupled to the memory. The processing circuitry is to implement the instructions to establish a wireless connection between the first wireless communication device and a second wireless communication device according to a wireless connectivity protocol, establish, using the wireless connectivity protocol, a location profile communication cluster including the first device and the second device, and within the communication cluster: process a message from the second device including location information and determine a provision of location services for the cluster based on the location information.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: April 30, 2019
    Assignee: Intel IP Corporation
    Inventors: Tirosh Levin, Chandru Aswani, Shidlingeshwar Khatakalle, Stefan Meyer, Haim Rochberger
  • Publication number: 20170057170
    Abstract: A mechanism is described for facilitating intelligent calibration and efficient performance of three-dimensional printers according to one embodiment. A method of embodiments, as described herein, includes receiving a printing request for three-dimensional (3D) printing of a 3D object, and monitoring a printing process to print the 3D object, where the printing process is performed based on a reference design associated with the 3D object, the reference design including expected measurements associated with the 3D object. The method may further include computing, in real-time during the printing process, actual measurements relating to the 3D object, where the actual measurements are obtained via one or more 3D cameras.
    Type: Application
    Filed: August 28, 2015
    Publication date: March 2, 2017
    Applicant: INTEL IP CORPORATION
    Inventors: Lalit Gupta, Shidlingeshwar Khatakalle