Patents by Inventor Shie Mannor

Shie Mannor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10339585
    Abstract: Systems and methods including one or more processing modules and one or more non-transitory storage modules storing computing instructions configured to run on the one or more processing modules and perform acts of receiving an online search query entered into a search field of an online ecommerce website by a user using the online ecommerce website, determining a query response to the online search query by combining a nonparametric bootstrap distribution and a mixture sequential probability ratio test, the query response comprising one or more products, and coordinating a display of the query response to the user using the online ecommerce website. The query response can be based on one of a query success rate per user session of a plurality of previous user sessions or a revenue per user session of the plurality of previous user sessions.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: July 2, 2019
    Assignee: WALMART APOLLO, LLC
    Inventors: Vineet Abhishek, Shie Mannor
  • Patent number: 10282462
    Abstract: A multi-modal computer classification network system for use in classifying data records is described herein. The system includes a memory device, a first classification computer server, a second classification computer server, and a policy computer server. The memory device includes an item records database and a labeling database. The first classification computer server includes a first classifier program that is configured to select an item record from the item database and generate a first classification record including a first ranked list of class labels. The second classification computer server includes a second classifier program that is configured to generate a second classification record including a second ranked list of class labels. The policy computer server includes a policy network that is programmed to determine a predicted class label based on the first and second ranked lists of class labels.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: May 7, 2019
    Assignee: WALMART APOLLO, LLC
    Inventors: Alessandro Magnani, Tom Ben Zion Zahavy, Abhinandan Krishnan, Shie Mannor
  • Publication number: 20180211303
    Abstract: Systems and methods including one or more processing modules and one or more non-transitory storage modules storing computing instructions configured to run on the one or more processing modules and perform acts of training a source classifier with labeled source training data of a first product category from a website of an online retailer, clustering target data for a second product category into a plurality of clusters, inserting into each cluster labeled source training data of the first product category, assigning a domain discriminator score to each cluster, determining whether each cluster comprises an agreement cluster or a disagreement cluster using the domain discriminator score, receiving a product search request for a product of the second category from a user of the web site, and coordinating a display of the product on the web site to promote the product.
    Type: Application
    Filed: January 23, 2017
    Publication date: July 26, 2018
    Applicant: WAL-MART STORES, INC.
    Inventors: Richard Edward Chatwin, Jaymin Daniel Mankowitz, Shie Mannor, Vineet Abhishek
  • Publication number: 20180121533
    Abstract: A multi-modal computer classification network system for use in classifying data records is described herein. The system includes a memory device, a first classification computer server, a second classification computer server, and a policy computer server. The memory device includes an item records database and a labeling database. The first classification computer server includes a first classifier program that is configured to select an item record from the item database and generate a first classification record including a first ranked list of class labels. The second classification computer server includes a second classifier program that is configured to generate a second classification record including a second ranked list of class labels. The policy computer server includes a policy network that is programmed to determine a predicted class label based on the first and second ranked lists of class labels.
    Type: Application
    Filed: October 31, 2016
    Publication date: May 3, 2018
    Inventors: Alessandro Magnani, Tom Ben Zion Zahavy, Abhinandan Krishnan, Shie Mannor
  • Publication number: 20180101885
    Abstract: Systems and methods including one or more processing modules and one or more non-transitory storage modules storing computing instructions configured to run on the one or more processing modules and perform acts of receiving an online search query entered into a search field of an online ecommerce website by a user using the online ecommerce website, determining a query response to the online search query by combining a nonparametric bootstrap distribution and a mixture sequential probability ratio test, the query response comprising one or more products, and coordinating a display of the query response to the user using the online ecommerce website. The query response can be based on one of a query success rate per user session of a plurality of previous user sessions or a revenue per user session of the plurality of previous user sessions.
    Type: Application
    Filed: October 6, 2016
    Publication date: April 12, 2018
    Applicant: WAL-MART STORES, INC.
    Inventors: Vineet Abhishek, Shie Mannor
  • Patent number: 9100153
    Abstract: A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: August 4, 2015
    Assignee: THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING/MCGILL UNIVERSITY
    Inventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani
  • Patent number: 8935195
    Abstract: Portable wireless devices are ubiquitous in modern society and many of these have integral sensors such as accelerometers, microphones, and Global Positioning Systems (GPS) that can collect data. This creates potential for intelligent applications to recognize the user, or aspects of the user and take appropriate action. According to embodiments of the invention there are presented techniques for representing such time series data which reduce the memory and computational complexity of performing the analysis and classifying the results. The techniques exploit time-delay embedding is to reconstruct the state and dynamics of an unknown dynamical system, Geometric Template Matching to build nonparametric classifiers, and algorithms to address the problem of selecting segments of data from which to build the time-delay models for classification problems.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: January 13, 2015
    Assignee: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Doina Precup, Jordan Frank, Shie Mannor
  • Patent number: 8898537
    Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. LDPC codes also offer error correction performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with the code length. They also offer challenges relating to the decoding complexity of the binary error-correction codes themselves and error floors limiting achievable bit-error rates. A new Relaxed Half-Stochastic (RHS) decoding algorithm is presented that reduces decoding complexity for high decoding throughput applications. The RHS algorithm uses an approach based on stochastic decoding algorithms but differs significantly from the conventional approaches of LDPC decoder implementation.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: November 25, 2014
    Assignee: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Warren Gross, Francois Leduc-Primeau, Saied Hemati, Shie Mannor
  • Patent number: 8677227
    Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with code length. They also offer challenges relating to decoding complexity and error floors limiting achievable bit-error rates.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: March 18, 2014
    Assignee: Royal Institution for the Advancement of Learning / McGill University
    Inventors: Warren Gross, Saied Hemati, Shie Mannor, Ali Naderi, Francois Leduc-Primeau
  • Publication number: 20120054576
    Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with code length. They also offer challenges relating to decoding complexity and error floors limiting achievable bit-error rates.
    Type: Application
    Filed: August 24, 2011
    Publication date: March 1, 2012
    Applicant: The Royal Institution for the Advancement of Learning / McGill University
    Inventors: Warren Gross, Saied Hemati, Shie Mannor, Ali Naderi, Francois Leduc-Primeau
  • Patent number: 8108758
    Abstract: The present invention relates to a decoding method and system for stochastic decoding of LDPC codes. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital bits. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the LDPC code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information bits. If an equality node is in a hold state a chosen bit is provided from a corresponding edge memory which is updated by storing output bits from the equality node when the same is in a state other than a hold state.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: January 31, 2012
    Assignee: McGill University
    Inventors: Warren J. Gross, Shie Mannor
  • Patent number: 8108760
    Abstract: A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: January 31, 2012
    Assignee: The Royal Institute for the Advancement of Learning/McGill University
    Inventors: Warren J. Gross, Shie Mannor, Gabi Sarkis
  • Patent number: 8095860
    Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: January 10, 2012
    Assignee: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani
  • Publication number: 20110293045
    Abstract: A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided.
    Type: Application
    Filed: June 1, 2011
    Publication date: December 1, 2011
    Applicant: The Royal Institution for the advancement of Learning/McGill University
    Inventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani
  • Publication number: 20110282828
    Abstract: Portable wireless devices are ubiquitous in modern society and many of these have integral sensors such as accelerometers, microphones, and Global Positioning Systems (GPS) that can collect data. This creates potential for intelligent applications to recognize the user, or aspects of the user and take appropriate action. According to embodiments of the invention there are presented techniques for representing such time series data which reduce the memory and computational complexity of performing the analysis and classifying the results. The techniques exploit time-delay embedding is to reconstruct the state and dynamics of an unknown dynamical system, Geometric Template Matching to build nonparametric classifiers, and algorithms to address the problem of selecting segments of data from which to build the time-delay models for classification problems.
    Type: Application
    Filed: May 11, 2011
    Publication date: November 17, 2011
    Applicant: The Royal Institution for the Advancement of Learning / McGill University
    Inventors: Doina Precup, Jordan Frank, Shie Mannor
  • Publication number: 20110231731
    Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. LDPC codes also offer error correction performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with the code length. They also offer challenges relating to the decoding complexity of the binary error-correction codes themselves and error floors limiting achievable bit-error rates. A new Relaxed Half-Stochastic (RHS) decoding algorithm is presented that reduces decoding complexity for high decoding throughput applications. The RHS algorithm uses an approach based on stochastic decoding algorithms but differs significantly from the conventional approaches of LDPC decoder implementation.
    Type: Application
    Filed: March 17, 2011
    Publication date: September 22, 2011
    Applicant: The Royal Institution for the Advancement of Learning / McGill University
    Inventors: Warren Gross, Francois Leduc-Primeau, Saied Hemati, Shie Mannor
  • Publication number: 20100074381
    Abstract: A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided.
    Type: Application
    Filed: September 25, 2009
    Publication date: March 25, 2010
    Applicant: The Royal Institution for the Advancement of Learning/ McGill University
    Inventors: Warren GROSS, Shie MANNOR, Saeed SHARIFI TEHRANI
  • Publication number: 20100017676
    Abstract: A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code.
    Type: Application
    Filed: July 15, 2009
    Publication date: January 21, 2010
    Applicant: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Warren J. GROSS, Shie MANNOR, Gabi SARKIS
  • Publication number: 20090100313
    Abstract: Disclosed is a pipelined iterative process and system. Data is received at an input port and is processed in a symbolwise fashion. Processing of each symbol is performed other than relying on completing the processing of an immediately preceding symbol such that operation of the system or process is independent of an order of the input symbols.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 16, 2009
    Applicant: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Warren J. GROSS, Shie MANNOR, Saeed SHARIFI TEHRANI
  • Publication number: 20080294970
    Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.
    Type: Application
    Filed: May 23, 2008
    Publication date: November 27, 2008
    Applicant: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani