Abstract: A method for making stacked metal plugs in via holes and contacts was achieved, while retaining alignment marks without using additional masking steps. The method involves the deposition of a barrier layer and a tungsten layer, which fill the via holes or contact openings in an insulating layer. The tungsten is then etched back, without overetching, to the surface of the barrier layer to form tungsten plugs that are coplanar with the surface of the insulating layer. Concurrently the tungsten is removed from the recessed alignment marks, which allows for the replication of the alignment marks in the next level of metal, thereby eliminating additional masking steps. The residual tungsten left on the surface after etch-back is removed by a short chemical/mechanical polishing to eliminate defects. The etch-back also removes the tungsten from the beveled edge of the substrate that can cause peeling and additional defects.

Abstract: A process for forming a MOS transistor having a salicide structure with a second gate spacers 36 and a source/drain/gate contact pads 32 33. A gate electrode 18 having first sidewall spacers 24 is formed on a substrate. Source and drain regions 28 are formed in the substrate. An amorphous silicon layer is formed over the substrate and patterned leaving the amorphous silicon layer over first sidewall spacers 24 and forming source/drain contact pads 33 over the source/drain regions and gate contact pads 32 over the gate electrode. Nitrogen ions are implanted vertically into the amorphous silicon layer 32 forming a nitrogen rich layer 34. The nitrogen rich layer 34 acts as an oxidation barrier source/drain an gate contact pads. The amorphous silicon layer 28 over the first sidewall spacer is oxidized using the nitrogen rich layer 34 as an oxidation barrier forming second gate spacers 36. A Ti layer is formed over the resultant surface.