Abstract: A convolutional neural network (CNN) operation accelerator comprising a first sub-accelerator and a second sub-accelerator is provided. The first sub-accelerator comprises I units of CNN processor cores, J units of element-wise & quantize processors, and K units of pool and nonlinear function processor. The second sub-accelerator comprises X units of CNN processor cores, Y units of first element-wise & quantize processors, and Z units of pool and nonlinear function processor. The above variables I˜K, X˜Z are all greater than 0, and at least one of the three relations, namely, “I is different from X”, “J is different from Y”, and “K is different from Z”, is satisfied. A to-be-performed CNN operation comprises a first partial CNN operation and a second partial CNN operation. The first sub-accelerator and the second sub-accelerator perform the first partial CNN operation and the second partial CNN operation, respectively.

Abstract: A convolutional neural-network calculating apparatus including a bidirectional-output operation module and a data scheduler is provided. The bidirectional-output operation module includes a number of bidirectional-output operators, a number of row-output accumulators, and a number of column-output accumulators. Each bidirectional-output operator has a row-output port and a column-output port. The row-output accumulators are coupled to the row-output ports, and the column-output accumulators are coupled to the corresponding column-output ports. The data scheduler is configured to provide a number of values of an input data and a number of convolution values of the convolution kernels to the bidirectional-output operators. In a first operation mode, the bidirectional-output operators output operation results to the corresponding column-output accumulators through the column-output ports.

Abstract: A verification system and a verification method for a neural network accelerator hardware are provided. The verification system for a neural network accelerator hardware includes a neural network graph compiler and an execution performance estimator. The neural network graph compiler is configured to receive an assumed neural network graph and convert the assumed neural network graph into a suggested inference neural network graph according to a hardware information and an operation mode. The execution performance estimator is configured to receive the suggested inference neural network graph and calculate an estimated performance of the neural network accelerator hardware according to a hardware calculation abstract information of the suggested inference neural network graph.

Abstract: A convolutional neural-network calculating apparatus including a bidirectional-output operation module and a data scheduler is provided. The bidirectional-output operation module includes a number of bidirectional-output operators, a number of row-output accumulators, and a number of column-output accumulators. Each bidirectional-output operator has a row-output port and a column-output port. The row-output accumulators are coupled to the row-output ports, and the column-output accumulators are coupled to the corresponding column-output ports. The data scheduler is configured to provide a number of values of an input data and a number of convolution values of the convolution kernels to the bidirectional-output operators. In a first operation mode, the bidirectional-output operators output operation results to the corresponding column-output accumulators through the column-output ports.

Abstract: A convolutional neural network (CNN) operation accelerator comprising a first sub-accelerator and a second sub-accelerator is provided. The first sub-accelerator comprises I units of CNN processor cores, J units of element-wise & quantize processors, and K units of pool and nonlinear function processor. The second sub-accelerator comprises X units of CNN processor cores, Y units of first element-wise & quantize processors, and Z units of pool and nonlinear function processor. The above variables I˜K, X˜Z are all greater than 0, and at least one of the three relations, namely, “I is different from X”, “J is different from Y”, and “K is different from Z”, is satisfied. A to-be-performed CNN operation comprises a first partial CNN operation and a second partial CNN operation. The first sub-accelerator and the second sub-accelerator perform the first partial CNN operation and the second partial CNN operation, respectively.

Abstract: A pulsed latching apparatus and a method for generating a pulse signal are provided. The pulsed latching apparatus consists of a pulsed latch and a pulse signal generator. A data input terminal of the pulsed latch receives input data, the pulsed latch latches the input data according to a pulse signal, and transmits the latched input data through the data output terminal to serve as output data. The pulse signal generator duplicates a data transmission delay between the data input terminal and the data output terminal of the pulsed latch to obtain a duplicated delay. The pulse signal generator receives a clock signal, and processes the clock signal according to the duplicated delay to generate the pulse signal.

Abstract: A level shifter transfers a first voltage signal to a second voltage signal. The level shifter comprises a comparison circuit, a delay circuit, and a selection circuit. The comparison circuit generates a first signal according to the comparison result between the first voltage signal and the reverse-phase signal of the first voltage signal. The delay circuit generates a second signal according to the first voltage signal. The selection circuit receives the first and the second signals and chooses the higher voltage one from the first signal and the second signal to be the second voltage signal.

Abstract: A level shifter transfers a first voltage signal to a second voltage signal. The level shifter comprises a comparison circuit, a delay circuit, and a selection circuit. The comparison circuit generates a first signal according to the comparison result between the first voltage signal and the reverse-phase signal of the first voltage signal. The delay circuit generates a second signal according to the first voltage signal. The selection circuit receives the first and the second signals and chooses the higher voltage one from the first signal and the second signal to be the second voltage signal.

Abstract: A pulsed latching apparatus and a method for generating a pulse signal are provided. The pulsed latching apparatus consists of a pulsed latch and a pulse signal generator. A data input terminal of the pulsed latch receives input data, the pulsed latch latches the input data according to a pulse signal, and transmits the latched input data through the data output terminal to serve as output data. The pulse signal generator duplicates a data transmission delay between the data input terminal and the data output terminal of the pulsed latch to obtain a duplicated delay. The pulse signal generator receives a clock signal, and processes the clock signal according to the duplicated delay to generate the pulse signal.