Patent number: 7608908
Abstract: Higher voltage device isolation structures (40, 60, 70, 80, 90, 90?) are provided for semiconductor integrated circuits having strongly doped buried layers (24, 24?). One or more dielectric lined deep isolation trenches (27, 27?, 27?, 27??) separates adjacent device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912). Electrical breakdown (BVdss) between the device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912) and the oppositely doped substrate (22, 22?) is found to occur preferentially where the buried layer (24, 24?) intersects the dielectric sidewalls (273, 274; 273?, 274?; 273?, 274?) of the trench (27, 27?, 27?, 27??). The breakdown voltage (BVdss) is increased by providing a more lightly doped region (42, 42?, 62, 72, 82) of the same conductivity type as the buried layer (24, 24?), underlying the buried layer (24, 24?) at the trench sidewalls (273, 274; 273?, 274?; 273?, 274?).
Type:
Grant
Filed:
May 22, 2008
Date of Patent:
October 27, 2009
Assignee:
Freescale Semiconductor, Inc.
Inventors:
Vishnu Khemka, Amitava Bose, Michael C. Butner, Bernhard H. Grote, Tahir A. Khan, Shifeng Shen, Ronghua Zhu