Patents by Inventor Shige Wang
Shige Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10572748Abstract: An adaptive parallel imaging processing system in a vehicle is provided. The system may include, but is not limited to, a plurality of processors and a resource management system including, but not limited to, an execution monitor, the execution monitor configured to calculate an average utilization of each of the plurality of processors over a moving window, and a service scheduler controlling a request queue for each of the plurality of processors, the service scheduler scheduling image processing tasks in the respective request queue for the each of the plurality of processors based upon the average utilization of each of the plurality of processors, the capabilities of each of the plurality of processors, and a priority associated with each image processing task, wherein an autonomous vehicle control system is configured to generate the instructions to control the at least one vehicle system based upon the processed image processing tasks.Type: GrantFiled: December 6, 2017Date of Patent: February 25, 2020Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Shige Wang, Wei Tong, Shuqing Zeng, Roman Millett
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Patent number: 10558539Abstract: Systems and methods are provided for testing a first computer device of a vehicle. A method includes selecting an operational component of the first computer device and selecting a test operation that is configured to utilize an entire capacity of the operational component. The method further includes instructing the first computer device to perform the test operation and to generate a first result. The method further yet includes retrieving a second result of the test operation and comparing the first result of the test operation from the first computer device with the second result. The method further yet includes indicating that the first computer device is faulty based at least in part on a difference between the first result and the second result.Type: GrantFiled: September 28, 2017Date of Patent: February 11, 2020Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Shige Wang, Gurmitsingh M. Banvait, Sidharth Nakra, Shane M. Boehner, Joseph G. D Ambrosio
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Publication number: 20190320115Abstract: Examples of techniques for dynamically selecting a batch size used in vehicle camera image processing are disclosed. In one example implementation, a method includes generating, by a processing device, a batch table and a mode table. The method further includes determining, by the processing device, image processing performance requirements for a current mode of a vehicle using the mode table, the vehicle comprising a plurality of cameras configured to capture a plurality of images. The method further includes selecting, by the processing device, a batch size and a processing frequency based at least in part on the image processing performance requirements for the current mode of the vehicle. The method further includes processing, by an accelerator, at least a subset of the plurality of images based at least in part on the batch size and processing frequency.Type: ApplicationFiled: April 11, 2018Publication date: October 17, 2019Inventors: Unmesh Dutta Bordoloi, Shige Wang, Stephen G. Lusko, Jinsong Wang
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Publication number: 20190302877Abstract: A method of controlling a vehicle includes determining a current operating situation of the vehicle, and identifying a subset of a plurality of sensors of the vehicle needed to provide data to enable a vehicle control function for the current operating situation of the vehicle. A remainder of the plurality of sensors is disengaged to reduce electric energy usage by the vehicle while the vehicle is operating in the current operating situation of the vehicle. A sampling rate for the selected subset of sensors may be reduced to further reduce energy usage of the vehicle. Additionally, an energy reduction processing strategy may be implemented to reduce a processor frequency or a voltage of a computing device used to provide the vehicle control function to further reduce energy usage of the vehicle.Type: ApplicationFiled: April 3, 2018Publication date: October 3, 2019Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Yiran Hu, Steven E. Muldoon, Wei Tong, Shige Wang
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Patent number: 10386899Abstract: Methods and systems are provided for controlling a temperature of a processor of a controller. In one embodiment, a method includes: identifying a status of at least one task of a plurality of software tasks performed on a first processor to be a hot task based on the software task's contribution to a temperature of the first processor; and selectively controlling the temperature of the first processor based on the identified status.Type: GrantFiled: August 8, 2017Date of Patent: August 20, 2019Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Shige Wang, Mark A. Zerbini, Unmesh Dutta Bordoloi, Soheil Samii, Massimo Osella
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Patent number: 10360079Abstract: A synchronization method in a multiprocessor system is provided. The method includes providing a plurality of synchronization mechanisms for synchronizing data to be accessed by a plurality of concurrently executable tasks, analyzing design information and runtime information for application software that includes the concurrently executable tasks, identifying, based on the analysis, software architecture patterns for the concurrently executable tasks that access a shared variable, and associating, based on the analysis, each of the software architecture patterns to one or more of the synchronization mechanisms.Type: GrantFiled: June 16, 2017Date of Patent: July 23, 2019Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Shige Wang, Stephen G. Lusko
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Publication number: 20190171895Abstract: An adaptive parallel imaging processing system in a vehicle is provided.Type: ApplicationFiled: December 6, 2017Publication date: June 6, 2019Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Shige Wang, Wei Tong, Shuqing Zeng, Roman Millett
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Publication number: 20190095302Abstract: Systems and methods are provided for testing a first computer device of a vehicle. A method includes selecting an operational component of the first computer device and selecting a test operation that is configured to utilize an entire capacity of the operational component. The method further includes instructing the first computer device to perform the test operation and to generate a first result. The method further yet includes retrieving a second result of the test operation and comparing the first result of the test operation from the first computer device with the second result. The method further yet includes indicating that the first computer device is faulty based at least in part on a difference between the first result and the second result.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Shige Wang, Gurmitsingh M. Banvait, Sidharth Nakra, Shane M. Boehner, Joseph G. D Ambrosio
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Publication number: 20190050032Abstract: Methods and systems are provided for controlling a temperature of a processor of a controller. In one embodiment, a method includes: identifying a status of at least one task of a plurality of software tasks performed on a first processor to be a hot task based on the software task's contribution to a temperature of the first processor; and selectively controlling the temperature of the first processor based on the identified status.Type: ApplicationFiled: August 8, 2017Publication date: February 14, 2019Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Shige Wang, Mark A. Zerbini, Unmesh Dutta Bordoloi, Soheil Samii, Massimo Osella
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Publication number: 20180365080Abstract: A synchronization method in a multiprocessor system is provided. The method includes providing a plurality of synchronization mechanisms for synchronizing data to be accessed by a plurality of concurrently executable tasks, analyzing design information and runtime information for application software that includes the concurrently executable tasks, identifying, based on the analysis, software architecture patterns for the concurrently executable tasks that access a shared variable, and associating, based on the analysis, each of the software architecture patterns to one or more of the synchronization mechanisms.Type: ApplicationFiled: June 16, 2017Publication date: December 20, 2018Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: SHIGE WANG, STEPHEN G. LUSKO
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Publication number: 20180295011Abstract: Disclosed are control algorithms and system architectures for managing operation of networked controllers and devices, including vehicles with an onboard network of electronic control units (ECU) and control logic for governing the snoozing and waking of these ECUs. A method for managing a motor vehicle's in-vehicle network of ECUs includes: determining status vectors for a group of the ECUs, each status vector indicating whether the corresponding ECU is awake or asleep; determining device roles for these ECUs—slave or master; determining an assigned hierarchy for selecting the ECUs as the master device; receiving a mode change signal indicating an ECU intends to transition to the asleep state or to the awake state; and, responsively, modifying the respective device role for one ECU from master to slave and the respective device role for another ECU from slave to master based on the assigned hierarchy and the status vectors for the ECUs.Type: ApplicationFiled: April 5, 2017Publication date: October 11, 2018Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Shige Wang, Chang Liu
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Publication number: 20180292988Abstract: A memory access method in a multicore processor integrated circuit (IC) is provided. The method comprises partitioning local memory on the IC into a plurality of memory regions wherein each memory region comprises one or more memory segments and assigning each memory region to one or more processing entities or applications wherein each processing entity comprises a processor core or a processing device that is under the control of a processor core and wherein the application is capable of being performed by one of the processing entities. The method further comprises monitoring, with each processing entity, the usage of each memory segment in each region assigned to the processing entity and assigned to the applications performed by the processing entity and swapping the data in a memory segment from a memory region experiencing a miss for desired data when the miss causes a data access with external memory.Type: ApplicationFiled: April 7, 2017Publication date: October 11, 2018Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: SHIGE WANG, J. DAVID ROSA
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Patent number: 9996431Abstract: A method of arbitrating conflicting outputs in a redundant control system. Execution data of a task executed by each controller in the redundant control system is recorded. The execution data includes an initial timestamp of each execution stream, identification of critical functions in each execution stream, and parameter values used by the critical functions. A path executed by each controller is identified based only on the critical functions executed for each execution stream. The recorded execution data of each executed path is applied to an arbitration module. An output result from one of the respective controllers selecting, by an arbitration module, based on the recorded execution data of each executed path. The output result of the selected controller is communicated to a next module for further processing.Type: GrantFiled: March 23, 2016Date of Patent: June 12, 2018Assignee: GM Global Technology Operations LLCInventors: Shige Wang, Xiaofeng F. Song, Xian Zhang
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Patent number: 9830270Abstract: A method of ordering memory access by an instruction cache of a central processing unit on a global memory device. A signal list of a link map file is extracted in the global memory device. Memory access traces relating to executed tasks are accessed from the signal list. Memory locations accessed in the global memory device from the access traces are identified. A correlation value for each pair of memory locations accessed in the global memory device is determined. Correlation values of the pairs of memory locations are determined, wherein the correlation values are computed based on a proximity of executable instructions utilizing the respective pair of memory locations. Accessed memory locations within the global memory device are reordered as a function of the determined correlation values. An executable file accessing the global memory device is modified.Type: GrantFiled: November 25, 2015Date of Patent: November 28, 2017Assignee: GM Global Technology Operations LLCInventors: Shuqing Zeng, Shige Wang, Stephen G. Lusko
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Publication number: 20170277604Abstract: A method of arbitrating conflicting outputs in a redundant control system. Execution data of a task executed by each controller in the redundant control system is recorded. The execution data includes an initial timestamp of each execution stream, identification of critical functions in each execution stream, and parameter values used by the critical functions. A path executed by each controller is identified based only on the critical functions executed for each execution stream. The recorded execution data of each executed path is applied to an arbitration module. An output result from one of the respective controllers selecting, by an arbitration module, based on the recorded execution data of each executed path. The output result of the selected controller is communicated to a next module for further processing.Type: ApplicationFiled: March 23, 2016Publication date: September 28, 2017Inventors: SHIGE WANG, XIAOFENG F. SONG, XIAN ZHANG
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Patent number: 9775035Abstract: A secure messaging communication system. A communication bus communicates messages between transmitting nodes. A secure hardware engine of a controller authenticates messages from requesting entities. A processor of the controller initially receives messages from the requesting entities. The processor includes a message request queue prioritizing received messages. The processor communicates a prioritized message from the request queue and associated authentication information to the secure hardware engine. The secure hardware engine authenticates the messages in response to receiving the prioritized messages and associated authentication information from the processor. The secure hardware engine communicates the authenticated messages to the processor for storage in a results queue.Type: GrantFiled: September 14, 2015Date of Patent: September 26, 2017Assignee: GM Global Technology Operations LLCInventors: Shige Wang, Stephen G. Lusko
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Publication number: 20170248995Abstract: Methods and systems are provided for controlling a temperature of a processor of a controller. In one embodiment, a method includes: collecting a first set of measurement data based on measurement parameters; processing the first set of measurement data associated with the processor using a predictor model to determine a temperature of the processor; and selectively controlling the temperature of the processor based on the determined temperature.Type: ApplicationFiled: February 29, 2016Publication date: August 31, 2017Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Shige WANG, Mark A. ZERBINI
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Patent number: 9720742Abstract: A system and method for accessing coherent data on a controller. The system and method include a first buffer and a second buffer that each may be read from or written to and an indicator that indicates which of the first or the second buffer is read from while the other of the first or second buffers is written to. The system and method also include a read synchronization protocol that allows the coherent data to be read from the buffer that the indicator indicates is the read buffer and a write synchronization protocol that allows the coherent data to be written to the buffer that the indicator indicates is the write buffer.Type: GrantFiled: May 15, 2014Date of Patent: August 1, 2017Assignee: GM Global Technology Operations LLCInventors: Shige Wang, Chang Liu, Trenton W. Haines, James T. Kurnik
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Publication number: 20170147495Abstract: A method of ordering memory access by an instruction cache of a central processing unit on a global memory device. A signal list of a link map file is extracted in the global memory device. Memory access traces relating to executed tasks are accessed from the signal list. Memory locations accessed in the global memory device from the access traces are identified. A correlation value for each pair of memory locations accessed in the global memory device is determined. Correlation values of the pairs of memory locations are determined, wherein the correlation values are computed based on a proximity of executable instructions utilizing the respective pair of memory locations. Accessed memory locations within the global memory device are reordered as a function of the determined correlation values. An executable file accessing the global memory device is modified.Type: ApplicationFiled: November 25, 2015Publication date: May 25, 2017Inventors: SHUQING ZENG, SHIGE WANG, STEPHEN G. LUSKO
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Publication number: 20170147402Abstract: A method of partitioning tasks on a multi-core ECU. A signal list of a link map file is extracted in a memory. Memory access traces relating to executed tasks are obtained from the ECU. A number of times each task accesses a memory location is identified. A correlation graph between the each task and each accessed memory location is generated. The correlation graph identifies a degree of linking relationship between each task and each memory location. The correlation graph is re-ordered so that the respective tasks and associated memory locations having greater degrees of linking relationships are adjacent to one another. The tasks are partitioned into a respective number of cores on the ECU. Allocating tasks and memory locations among the respective number of cores is performed as a function of substantially balancing workloads with minimum cross-core communication among the respective cores.Type: ApplicationFiled: November 25, 2015Publication date: May 25, 2017Inventors: SHUQING ZENG, SHIGE WANG, STEPHEN G. LUSKO