Abstract: A memory access method in a multicore processor integrated circuit (IC) is provided. The method comprises partitioning local memory on the IC into a plurality of memory regions wherein each memory region comprises one or more memory segments and assigning each memory region to one or more processing entities or applications wherein each processing entity comprises a processor core or a processing device that is under the control of a processor core and wherein the application is capable of being performed by one of the processing entities. The method further comprises monitoring, with each processing entity, the usage of each memory segment in each region assigned to the processing entity and assigned to the applications performed by the processing entity and swapping the data in a memory segment from a memory region experiencing a miss for desired data when the miss causes a data access with external memory.

Abstract: Disclosed are control algorithms and system architectures for managing operation of networked controllers and devices, including vehicles with an onboard network of electronic control units (ECU) and control logic for governing the snoozing and waking of these ECUs. A method for managing a motor vehicle's in-vehicle network of ECUs includes: determining status vectors for a group of the ECUs, each status vector indicating whether the corresponding ECU is awake or asleep; determining device roles for these ECUs—slave or master; determining an assigned hierarchy for selecting the ECUs as the master device; receiving a mode change signal indicating an ECU intends to transition to the asleep state or to the awake state; and, responsively, modifying the respective device role for one ECU from master to slave and the respective device role for another ECU from slave to master based on the assigned hierarchy and the status vectors for the ECUs.

Abstract: A method of arbitrating conflicting outputs in a redundant control system. Execution data of a task executed by each controller in the redundant control system is recorded. The execution data includes an initial timestamp of each execution stream, identification of critical functions in each execution stream, and parameter values used by the critical functions. A path executed by each controller is identified based only on the critical functions executed for each execution stream. The recorded execution data of each executed path is applied to an arbitration module. An output result from one of the respective controllers selecting, by an arbitration module, based on the recorded execution data of each executed path. The output result of the selected controller is communicated to a next module for further processing.

Abstract: A method of ordering memory access by an instruction cache of a central processing unit on a global memory device. A signal list of a link map file is extracted in the global memory device. Memory access traces relating to executed tasks are accessed from the signal list. Memory locations accessed in the global memory device from the access traces are identified. A correlation value for each pair of memory locations accessed in the global memory device is determined. Correlation values of the pairs of memory locations are determined, wherein the correlation values are computed based on a proximity of executable instructions utilizing the respective pair of memory locations. Accessed memory locations within the global memory device are reordered as a function of the determined correlation values. An executable file accessing the global memory device is modified.

Abstract: A method of arbitrating conflicting outputs in a redundant control system. Execution data of a task executed by each controller in the redundant control system is recorded. The execution data includes an initial timestamp of each execution stream, identification of critical functions in each execution stream, and parameter values used by the critical functions. A path executed by each controller is identified based only on the critical functions executed for each execution stream. The recorded execution data of each executed path is applied to an arbitration module. An output result from one of the respective controllers selecting, by an arbitration module, based on the recorded execution data of each executed path. The output result of the selected controller is communicated to a next module for further processing.

Abstract: A secure messaging communication system. A communication bus communicates messages between transmitting nodes. A secure hardware engine of a controller authenticates messages from requesting entities. A processor of the controller initially receives messages from the requesting entities. The processor includes a message request queue prioritizing received messages. The processor communicates a prioritized message from the request queue and associated authentication information to the secure hardware engine. The secure hardware engine authenticates the messages in response to receiving the prioritized messages and associated authentication information from the processor. The secure hardware engine communicates the authenticated messages to the processor for storage in a results queue.

Abstract: Methods and systems are provided for controlling a temperature of a processor of a controller. In one embodiment, a method includes: collecting a first set of measurement data based on measurement parameters; processing the first set of measurement data associated with the processor using a predictor model to determine a temperature of the processor; and selectively controlling the temperature of the processor based on the determined temperature.

Abstract: A system and method for accessing coherent data on a controller. The system and method include a first buffer and a second buffer that each may be read from or written to and an indicator that indicates which of the first or the second buffer is read from while the other of the first or second buffers is written to. The system and method also include a read synchronization protocol that allows the coherent data to be read from the buffer that the indicator indicates is the read buffer and a write synchronization protocol that allows the coherent data to be written to the buffer that the indicator indicates is the write buffer.

Abstract: A method of ordering memory access by an instruction cache of a central processing unit on a global memory device. A signal list of a link map file is extracted in the global memory device. Memory access traces relating to executed tasks are accessed from the signal list. Memory locations accessed in the global memory device from the access traces are identified. A correlation value for each pair of memory locations accessed in the global memory device is determined. Correlation values of the pairs of memory locations are determined, wherein the correlation values are computed based on a proximity of executable instructions utilizing the respective pair of memory locations. Accessed memory locations within the global memory device are reordered as a function of the determined correlation values. An executable file accessing the global memory device is modified.

Abstract: A method of partitioning tasks on a multi-core ECU. A signal list of a link map file is extracted in a memory. Memory access traces relating to executed tasks are obtained from the ECU. A number of times each task accesses a memory location is identified. A correlation graph between the each task and each accessed memory location is generated. The correlation graph identifies a degree of linking relationship between each task and each memory location. The correlation graph is re-ordered so that the respective tasks and associated memory locations having greater degrees of linking relationships are adjacent to one another. The tasks are partitioned into a respective number of cores on the ECU. Allocating tasks and memory locations among the respective number of cores is performed as a function of substantially balancing workloads with minimum cross-core communication among the respective cores.

Abstract: A method of adaptively reconfiguring controller functions during a frame overrun. A frame overrun condition is detected. A respective task from a plurality of tasks is identified as a largest contributor to the frame overrun. A mode associated with the identified task is identified to correct the frame overrun. Functions are reallocated within the identified task to one or more other tasks until the frame overrun condition is corrected. Respective functions reallocated are identified as a function of the identified mode.

Abstract: A secure messaging communication system. A communication bus communicates messages between transmitting nodes. A secure hardware engine of a controller authenticates messages from requesting entities. A processor of the controller initially receives messages from the requesting entities. The processor includes a message request queue prioritizing received messages. The processor communicates a prioritized message from the request queue and associated authentication information to the secure hardware engine. The secure hardware engine authenticates the messages in response to receiving the prioritized messages and associated authentication information from the processor. The secure hardware engine communicates the authenticated messages to the processor for storage in a results queue.

Abstract: A lane centering fusion system including a primary controller determining whether a vehicle is centered within a lane of travel. The primary controller includes a primary lane fusion unit for fusing lane sensed data for identifying a lane center position. A secondary controller determines whether a vehicle is centered within a lane of travel. The secondary controller includes a secondary lane fusion unit for fusing lane sensed data for identifying the lane center position. The primary controller and secondary controller are asynchronous controllers. A lane centering control unit maintains the vehicle centered within the lane of travel. The lane centering control unit utilizes fusion data output from the primary controller for maintaining lane centering control. The lane centering control unit utilizes fusion data output from the secondary controller in response to a detection of a fault with respect to the primary controller.

Abstract: A method and architecture of reconfiguring software mode management for a system. A prior status mode of a subsystem is identified. The primary controller includes a primary software algorithm for maintaining operations of the subsystem. A mode determination logic function is retrieved in a table for determining whether a mode change occurred. The mode determination logic function associated with the prior mode is executed. A current mode is determined from the table based on results from the execution of the mode determination logic function. An action list associated with the identified current mode in the table is identified. The action list identifies functions for transitioning the nodes from the prior mode to the current node. An action list associated with the current mode including a list of action functions for transitioning the previous mode to the current mode is executed. The table is independently modifiable from the primary software mode management algorithm.

Abstract: A method of adaptively reconfiguring controller functions during a frame overrun. A frame overrun condition is detected. A respective task from a plurality of tasks is identified as a largest contributor to the frame overrun. A mode associated with the identified task is identified to correct the frame overrun. Functions are reallocated within the identified task to one or more other tasks until the frame overrun condition is corrected. Respective functions reallocated are identified as a function of the identified mode.

Abstract: A method and architecture of reconfiguring software mode management for a system. A prior status mode of a subsystem is identified. The primary controller includes a primary software algorithm for maintaining operations of the subsystem. A mode determination logic function is retrieved in a table for determining whether a mode change occurred. The mode determination logic function associated with the prior mode is executed. A current mode is determined from the table based on results from the execution of the mode determination logic function. An action list associated with the identified current mode in the table is identified. The action list identifies functions for transitioning the nodes from the prior mode to the current node. An action list associated with the current mode including a list of action functions for transitioning the previous mode to the current mode is executed. The table is independently modifiable from the primary software mode management algorithm.

Abstract: A system and method for reconfigurable inter-processor communications in a controller. The system and method include providing multiple processors in the controller and generating a send buffer and a receive buffer for each of the processors. The system and method further include generating a send table and a receive table for each of the processors where the send table stores identifying information about messages being sent and where the receive table stores identifying information about messages being received, and providing infrastructure services that include protocols for sending and receiving messages between multiple processors in the controller.

Abstract: A lane centering fusion system including a primary controller determining whether a vehicle is centered within a lane of travel. The primary controller includes a primary lane fusion unit for fusing lane sensed data for identifying a lane center position. A secondary controller determines whether a vehicle is centered within a lane of travel. The secondary controller includes a secondary lane fusion unit for fusing lane sensed data for identifying the lane center position. The primary controller and secondary controller are asynchronous controllers. A lane centering control unit maintains the vehicle centered within the lane of travel. The lane centering control unit utilizes fusion data output from the primary controller for maintaining lane centering control. The lane centering control unit utilizes fusion data output from the secondary controller in response to a detection of a fault with respect to the primary controller.

Abstract: A method of establishing traceability for embedded software systems. A design code database is provided for an embedded software system. A test suite database including a plurality of test cases is structured for testing design code of the embedded software system. The structuring of the test cases provides a correspondence from a respective test case to a respective portion of the design code. A processor receives a design code modification to the embedded software. An associated test case is identified for testing the modified design code being based on traceability data. The associated test case is revised to accommodate the modified design code. The modified test cases are integrated into the test suite. A traceability database establishes a one-to-one correspondence between the modified design coder and the modified test case is updated.

Abstract: A system and method for reconfigurable inter-processor communications in a controller. The system and method include providing multiple processors in the controller and generating a send buffer and a receive buffer for each of the processors. The system and method further include generating a send table and a receive table for each of the processors where the send table stores identifying information about messages being sent and where the receive table stores identifying information about messages being received, and providing infrastructure services that include protocols for sending and receiving messages between multiple processors in the controller.