Patents by Inventor Shigeaki Hayase

Shigeaki Hayase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240290874
    Abstract: A semiconductor device includes a semiconductor layer including an element region, and a termination region; a first electrode; a second electrode; a semi-insulating film located on the termination region; an insulating film located between the semiconductor layer and the semi-insulating film; and a protective film located on the semi-insulating film. The insulating film includes an inner perimeter portion, the inner perimeter portion being located between an end portion of the first electrode positioned at the termination region side and an end portion of the second semiconductor part positioned at the termination region side, an outer perimeter portion located between the second electrode and the semiconductor layer, and an intermediate portion located between the inner perimeter portion and the outer perimeter portion. A thickness of the intermediate portion is less than a thickness of the inner perimeter portion and a thickness of the outer perimeter portion.
    Type: Application
    Filed: August 3, 2023
    Publication date: August 29, 2024
    Inventors: Kazushi MAEDA, Ryohei GEJO, Shigeaki HAYASE
  • Patent number: 11824056
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes, a control electrode and a control interconnect. The semiconductor part includes first to sixth layers and is provided between the first and second electrodes. The second layer is provided between the first layer and the second electrode. The third layer is provided between the second layer and the second electrode. The fourth and fifth layers are arranged between the first layer and the first electrode. The second electrode and the control interconnect are arranged on the semiconductor part. The control electrode is provided between the second electrode and the semiconductor part. The sixth layer is provided between the first layer and the control interconnect. The fifth semiconductor layer is provided between the first electrode and the sixth layer. The first semiconductor layer includes a carrier trap provided between the fifth and sixth layers.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: November 21, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Ryohei Gejo, Akiyo Minamikawa, Shigeaki Hayase
  • Publication number: 20230307513
    Abstract: A semiconductor device includes a semiconductor layer, a conductive film, a first insulating film, and a second insulating film. The semiconductor layer has an element region where a semiconductor element is provided and a termination region surrounding the element region. The conductive film is provided on the element region and the termination region. The first insulating film is provided on the conductive film on the termination region and a portion of the element region adjacent to the termination region. The second insulating film that is lower in resistivity than the first insulating film, and higher in resistivity than the conductive film, is provided on the first insulating film.
    Type: Application
    Filed: September 1, 2022
    Publication date: September 28, 2023
    Inventors: Emiko INOUE, Motoya KISHIDA, Shigeaki HAYASE, Kazushi MAEDA
  • Publication number: 20220246606
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes, a control electrode and a control interconnect. The semiconductor part includes first to sixth layers and is provided between the first and second electrodes. The second layer is provided between the first layer and the second electrode. The third layer is provided between the second layer and the second electrode. The fourth and fifth layers are arranged between the first layer and the first electrode. The second electrode and the control interconnect are arranged on the semiconductor part. The control electrode is provided between the second electrode and the semiconductor part. The sixth layer is provided between the first layer and the control interconnect. The fifth semiconductor layer is provided between the first electrode and the sixth layer. The first semiconductor layer includes a carrier trap provided between the fifth and sixth layers.
    Type: Application
    Filed: September 10, 2021
    Publication date: August 4, 2022
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Ryohei GEJO, Akiyo MINAMIKAWA, Shigeaki HAYASE
  • Patent number: 10811337
    Abstract: A semiconductor device includes a first electrode plate, a second electrode plate disposed to oppose the first electrode plate, and a semiconductor chip disposed between the first electrode plate and the second electrode plate. At least one of the first electrode plate and the second electrode plate has a space where a cooling medium circulates.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 20, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Shigeaki Hayase
  • Publication number: 20200058574
    Abstract: A semiconductor device includes a first electrode plate, a second electrode plate disposed to oppose the first electrode plate, and a semiconductor chip disposed between the first electrode plate and the second electrode plate. At least one of the first electrode plate and the second electrode plate has a space where a cooling medium circulates.
    Type: Application
    Filed: January 28, 2019
    Publication date: February 20, 2020
    Inventor: Shigeaki Hayase
  • Patent number: 10020391
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer; a plurality of semiconductor regions; second semiconductor region; a first electrode being positioned between the plurality of first semiconductor regions, the first electrode contacting with the semiconductor layer, each of the plurality of first semiconductor regions, and the second semiconductor region via a first insulating film; a second electrode provided below the first electrode, and contacting with the semiconductor layer via a second insulating film; an insulating layer interposed between the first electrode and the second electrode; a third electrode electrically connected to the semiconductor layer; and a fourth electrode connected to the second semiconductor region. The first electrode has a first portion and a pair of second portions. And each of the pair of second portions is provided along the first insulating film.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: July 10, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeru Matsuoka, Nobuyuki Sato, Shigeaki Hayase, Kentaro Ichinoseki
  • Patent number: 9953902
    Abstract: A semiconductor device includes first and second conductive layers on a substrate and separated from each other. A first semiconductor chip is mounted on the first conductive layer and has a first electrode on a side opposite the first conductive layer. A second semiconductor chip is mounted on the first conductive layer and has a second electrode on a side opposite the first conductive layer. A first metal member is mounted on the first electrode. A second metal member is mounted on the second electrode. A metal plate has a first portion disposed on the first and second metal members, and a second portion connected to the second conductive layer. The metal plate electrically connects the first and second electrodes to the second conductive layer through the first and second metal members.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: April 24, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeaki Hayase, Hiroshi Matsuyama
  • Publication number: 20170271247
    Abstract: A semiconductor device includes first and second conductive layers on a substrate and separated from each other. A first semiconductor chip is mounted on the first conductive layer and has a first electrode on a side opposite the first conductive layer. A second semiconductor chip is mounted on the first conductive layer and has a second electrode on a side opposite the first conductive layer. A first metal member is mounted on the first electrode. A second metal member is mounted on the second electrode. A metal plate has a first portion disposed on the first and second metal members, and a second portion connected to the second conductive layer. The metal plate electrically connects the first and second electrodes to the second conductive layer through the first and second metal members.
    Type: Application
    Filed: August 29, 2016
    Publication date: September 21, 2017
    Inventors: Shigeaki HAYASE, Hiroshi MATSUYAMA
  • Publication number: 20150021685
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer; a plurality of semiconductor regions; second semiconductor region; a first electrode being positioned between the plurality of first semiconductor regions, the first electrode contacting with the semiconductor layer, each of the plurality of first semiconductor regions, and the second semiconductor region via a first insulating film; a second electrode provided below the first electrode, and contacting with the semiconductor layer via a second insulating film; an insulating layer interposed between the first electrode and the second electrode; a third electrode electrically connected to the semiconductor layer; and a fourth electrode connected to the second semiconductor region. The first electrode has a first portion and a pair of second portions. And each of the pair of second portions is provided along the first insulating film.
    Type: Application
    Filed: October 9, 2014
    Publication date: January 22, 2015
    Inventors: Takeru MATSUOKA, Nobuyuki SATO, Shigeaki HAYASE, Kentaro ICHINOSEKI
  • Patent number: 8884362
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer; a plurality of semiconductor regions; second semiconductor region; a first electrode being positioned between the plurality of first semiconductor regions, the first electrode contacting with the semiconductor layer, each of the plurality of first semiconductor regions, and the second semiconductor region via a first insulating film; a second electrode provided below the first electrode, and contacting with the semiconductor layer via a second insulating film; an insulating layer interposed between the first electrode and the second electrode; a third electrode electrically connected to the semiconductor layer; and a fourth electrode connected to the second semiconductor region. The first electrode has a first portion and a pair of second portions. And each of the pair of second portions is provided along the first insulating film.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: November 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeru Matsuoka, Nobuyuki Sato, Shigeaki Hayase, Kentaro Ichinoseki
  • Publication number: 20130113039
    Abstract: A semiconductor device provides a MOSFET having first and second regions. In the first region, a plurality of unit cells of the MOSFET device are provided. At the end of the plurality of the unit cells, a termination cell is provided. An n type layer underlies the unit cells, between the unit cells and an underlying electrode. In the unit cell region, this n doped layer is dually doped with impurities at two different densities, whereas, adjacent the termination cell, a different paradigm is provided. In one aspect, only one of the two n doped layers extends along a side of the termination cell. In a second aspect, the termination unit is in contact with an oppositely doped layer as compared to the impurities in the dual doped layer. In this way, breakdown voltage may be maintained while on-resistance is simultaneously reduced.
    Type: Application
    Filed: September 7, 2012
    Publication date: May 9, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeru MATSUOKA, Kentaro ICHINOSEKI, Shigeaki HAYASE, Nobuyuki SATO
  • Patent number: 8410546
    Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode provided in the second trench. The trench source electrode is shaped like a stripe and connected to the source electrode through its longitudinal portion.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: April 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kawaguchi, Miwako Akiyama, Yoshihiro Yamaguchi, Nobuyuki Sato, Shigeaki Hayase
  • Publication number: 20130069150
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer; a plurality of semiconductor regions; second semiconductor region; a first electrode being positioned between the plurality of first semiconductor regions, the first electrode contacting with the semiconductor layer, each of the plurality of first semiconductor regions, and the second semiconductor region via a first insulating film; a second electrode provided below the first electrode, and contacting with the semiconductor layer via a second insulating film; an insulating layer interposed between the first electrode and the second electrode; a third electrode electrically connected to the semiconductor layer; and a fourth electrode connected to the second semiconductor region. The first electrode has a first portion and a pair of second portions. And each of the pair of second portions is provided along the first insulating film.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 21, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeru MATSUOKA, Nobuyuki Sato, Shigeaki Hayase, Kentaro Ichinoseki
  • Publication number: 20090242977
    Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode provided in the second trench. The trench source electrode is shaped like a stripe and connected to the source electrode through its longitudinal portion.
    Type: Application
    Filed: March 20, 2009
    Publication date: October 1, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke KAWAGUCHI, Miwako Akiyama, Yoshihiro Yamaguchi, Nobuyuki Sato, Shigeaki Hayase
  • Patent number: RE46204
    Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode provided in the second trench. The trench source electrode is shaped like a stripe and connected to the source electrode through its longitudinal portion.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: November 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kawaguchi, Miwako Akiyama, Yoshihiro Yamaguchi, Nobuyuki Sato, Shigeaki Hayase