Patents by Inventor Shigeaki Iwasa
Shigeaki Iwasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9081711Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.Type: GrantFiled: November 26, 2013Date of Patent: July 14, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kenta Yasufuku, Shigeaki Iwasa, Yasuhiko Kurosawa, Hiroo Hayashi, Seiji Maeda, Mitsuo Saito
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Patent number: 8949572Abstract: An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.Type: GrantFiled: October 16, 2009Date of Patent: February 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiko Kurosawa, Shigeaki Iwasa, Seiji Maeda, Nobuhiro Yoshida, Mitsuo Saito, Hiroo Hayashi
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Publication number: 20140164702Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.Type: ApplicationFiled: November 26, 2013Publication date: June 12, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenta Yasufuku, Shigeaki Iwasa, Yasuhiko Kurosawa, Hiroo Hayashi, Seiji Maeda, Mitsuo Saito
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Publication number: 20140082263Abstract: According to one embodiment, a memory system includes a plurality of nonvolatile memories, an address converter, a plurality of channel controllers, and a controller. The plurality of nonvolatile memories is connected to respective channels. The address converter converts a logical address of a read request into a physical address of the nonvolatile memories. Each of the channel controllers is provided to each of the channels. Each of the channel controllers has a plurality of queues, each queues stores at least two read request. The controller selects a queue which stores no read request, and transfers the read request to the selected queue.Type: ApplicationFiled: September 20, 2011Publication date: March 20, 2014Inventors: Shigeaki Iwasa, Kohei Oikawa
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Patent number: 8607024Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.Type: GrantFiled: December 1, 2010Date of Patent: December 10, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kenta Yasufuku, Shigeaki Iwasa, Yasuhiko Kurosawa, Hiroo Hayashi, Seiji Maeda, Mitsuo Saito
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Patent number: 8332447Abstract: Systems and methods for performing multiplication of fixed-point fractional values with the same throughput as addition and subtraction operations, and without loss of accuracy in the result. In one embodiment, a method includes reading data from a pair of source registers that contains multiple single-width multiplicand values. Each multiplicand value in one of the source registers is paired with a corresponding multiplicand value in the other source register. For each pair of multiplicands, a double-width product is generated, then a single-width portion of the product is selected and stored in a target register. The selection of the single-width portion is performed by shifting the double-width products in funnel shifters. The immediate shifting of the double-width products to select the single-width portions allows the operation to achieve the same throughput as addition and subtraction operations.Type: GrantFiled: September 8, 2009Date of Patent: December 11, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Shigeaki Iwasa
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Patent number: 8145804Abstract: A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.Type: GrantFiled: September 21, 2009Date of Patent: March 27, 2012Assignees: Kabushiki Kaisha Toshiba, International Business Machines CorporationInventors: Brian King Flachs, Brad William Michael, Nicolas Maeding, Shigeaki Iwasa, Seiji Maeda, Hiroo Hayashi
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Publication number: 20110231593Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.Type: ApplicationFiled: December 1, 2010Publication date: September 22, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenta YASUFUKU, Shigeaki IWASA, Yasuhiko KUROSAWA, Hiroo HAYASHI, Seiji MAEDA, Mitsuo SAITO
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Publication number: 20110072170Abstract: A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.Type: ApplicationFiled: September 21, 2009Publication date: March 24, 2011Inventors: Brian King Flachs, Brad William Michael, Nicolas Maeding, Shigeaki Iwasa, Seiji Maeda, Hiroo Hayashi
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Publication number: 20110060781Abstract: Systems and methods for performing multiplication of fixed-point fractional values with the same throughput as addition and subtraction operations, and without loss of accuracy in the result. In one embodiment, a method includes reading data from a pair of source registers that contains multiple single-width multiplicand values. Each multiplicand value in one of the source registers is paired with a corresponding multiplicand value in the other source register. For each pair of multiplicands, a double-width product is generated, then a single-width portion of the product is selected and stored in a target register. The selection of the single-width portion is performed by shifting the double-width products in funnel shifters. The immediate shifting of the double-width products to select the single-width portions allows the operation to achieve the same throughput as addition and subtraction operations.Type: ApplicationFiled: September 8, 2009Publication date: March 10, 2011Inventor: Shigeaki Iwasa
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Publication number: 20100100684Abstract: A set associative cache memory includes a tag memory configured to store tags which are predetermined high-order bits of an address, a tag comparator configured to compare a tag in a request address (RA) with the tag stored in the tag memory and a data memory configured to incorporate way information obtained through a comparison by the tag comparator in part of a column address.Type: ApplicationFiled: October 16, 2009Publication date: April 22, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Yasuhiko Kurosawa, Atsushi Kameyama, Shigeaki Iwasa, Hiroo Hayashi, Mitsuo Saito
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Publication number: 20100100685Abstract: An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.Type: ApplicationFiled: October 16, 2009Publication date: April 22, 2010Applicant: Kabushihiki Kaisha ToshibaInventors: Yasuhiko Kurosawa, Shigeaki Iwasa, Seiji Maeda, Nobuhiro Yoshida, Mitsuo Saito, Hiroo Hayashi
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Patent number: 7657798Abstract: A semiconductor integrated circuit has a cell array, a redundancy cell capable of replacing a defective cell, a redundancy control circuit, a plurality of first fuses, a plurality of second fuses, a plurality of third fuses, a first shift register configured to hold states of the plurality of first fuses, a second shift register configured to be connected in cascade to the first shift register and to hold states of the plurality of second fuses, a third shift register configured to be connected to the first and second shift registers in cascade and to hold states of the plurality of third fuses, a CRC remainder calculator configured to sequentially input information held by the first to third shift registers to a CRC generating equation to calculate a remainder obtained by division, and a CRC determination part that outputs information indicative of whether the first to third fuses are correctly programmed.Type: GrantFiled: December 27, 2006Date of Patent: February 2, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Natsuki Kushiyama, Shigeaki Iwasa
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Publication number: 20070226552Abstract: A semiconductor integrated circuit has a cell array, a redundancy cell capable of replacing a defective cell, a redundancy control circuit, a plurality of first fuses programmed in accordance with identification information for specifying a chip mounting the cell array, a plurality of second fuses programmed in accordance with the redundancy information for replacing the defective memory cell with the redundancy cell and various setting information of the chip, a plurality of third fuses programmed in accordance with a CRC code generated based on the redundancy information, various setting information of the chip and the identification information, a first shift register configured to hold states of the plurality of first fuses, a second shift register configured to be connected in cascade to the first shift register and to hold states of the plurality of second fuses, a third shift register configured to be connected to the first and second shift registers in cascade and to hold states of the plurality of thType: ApplicationFiled: December 27, 2006Publication date: September 27, 2007Inventors: Natsuki Kushiyama, Shigeaki Iwasa
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Patent number: 6742142Abstract: The present invention is to provide an emulator and a method of emulation for using testing a system having complex interfaces capable of stable testing can be realize under the system regulation frequency or less frequency without using the high-performance and expensive tester. The emulator comprises a content addressable memory (CAM) configured to store addresses accessed by a system to be tested, a memory unit having storage area corresponding to the entry of the CAM, configured to store data corresponding to the address stored in the CAM, and test information for emulation, a shift register configured to store data and test information from a tester and transfer the data and the test information to the CAM and the memory unit, and a state machine configured to receive a request from a system or a tester and control transferring between a system and a tester.Type: GrantFiled: December 27, 2000Date of Patent: May 25, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Mikio Takasugi, Shigeaki Iwasa
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Publication number: 20030061529Abstract: Provided is a computer system which includes a CPU configured to execute instructions, a timing generator configured to provide an internal clock, and a selector configured to receive an external clock and the internal clock and to select any one of the external clock and the internal clock as a read-out timing signal with respect to an external memory device which stores an instruction to be executed initially after a power source is turned on.Type: ApplicationFiled: September 25, 2002Publication date: March 27, 2003Inventor: Shigeaki Iwasa
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Publication number: 20010016922Abstract: The present invention is to provide an emulator and a method of emulation for using testing a system having complex interfaces capable of stable testing can be realize under the system regulation frequency or less frequency without using the high-performance and expensive tester. The emulator comprises a content addressable memory (CAM) configured to store addresses accessed by a system to be tested, a memory unit having storage area corresponding to the entry of the CAM, configured to store data corresponding to the address stored in the CAM, and test information for emulation, a shift register configured to store data and test information from a tester and transfer the data and the test information to the CAM and the memory unit, and a state machine configured to receive a request from a system or a tester and control transferring between a system and a tester.Type: ApplicationFiled: December 27, 2000Publication date: August 23, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mikio Takasugi, Shigeaki Iwasa
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Patent number: 5522058Abstract: A distributed shared-memory multiprocessor system capable of reducing a traffic on the shared bus, without imposing any constraint concerning the types of variables to be accessed in the parallel programs, such that a high system extensibility can be realized. The system is formed by a plurality of processor units coupled through a shared bus, where each processor unit comprises: a CPU; a main memory connected with the CPU through an internal bus, for storing a distributed part of data entries of a shared-memory of the system; a cache memory associated with the CPU and connected with the main memory through the internal bus, for caching selected data entries of the shared-memory; and a sharing management unit connected with the main memory and the cache memory through the internal bus, For interfacing the internal bus and the shared bus according to a sharing state for each data entry of the main memory and a cache state of each data entry of the cache memory.Type: GrantFiled: August 11, 1993Date of Patent: May 28, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Shigeaki Iwasa, Takashi Omizo
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Patent number: 5241641Abstract: A hierarchical cache memory apparatus assembled in a multiprocessor computer system including a plurality of processors and a memory device, includes a plurality of first cache memory devices arranged in correspondence with the plurality of processors and each including a controller including a first status identification section for identifying status of each of a plurality of pieces of address information, a plurality of first connection devices for connecting the plurality of first cache memory devices in units of a predetermined number of devices to constitute a plurality of mini-cluster devices a plurality of second cache memory devices respectively connected to the first connection devices in correspondence with the plurality of mini-cluster devices, having all the addresses of address information of the plurality of first cache memory devices in the mini-cluster devices, and each comprising a controller including a second status identification section for identifying status of each of the plurality ofType: GrantFiled: March 28, 1990Date of Patent: August 31, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Shigeaki Iwasa, Satoru Hashimoto, Shigehiro Asano
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Patent number: 5177701Abstract: A computer for performing immediate calculations by executing an immediate calculation instruction containing a first immediate value and an immediate prefixed instruction containing a second immediate value consists of a register for storing the second immediate value, a prefix state flag for setting a flag in cases where the second immediate value is stored in the register, concatenating unit for concatenating the first immediate value with the second immediate value in cases where the flag in the prefix state flag is set and generating the concatenated immediate value as a first constant, bit extension unit for extending the number of bits in the first immediate value without changing the first immediate value and generating the extended immediate value as a second constant, selector for selecting the first constant generated in the concatenating unit in cases where the flag in the prefix state flag is set and selecting the second constant generated in the bit extension unit in cases where the flag in theType: GrantFiled: November 6, 1991Date of Patent: January 5, 1993Assignee: Kabushiki Kaisha ToshibaInventor: Shigeaki Iwasa