Patents by Inventor Shigeaki Kawamata
Shigeaki Kawamata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180059712Abstract: A wireless communication apparatus includes a memory, and a processor coupled to the memory and configured to calculate a variation amount based on a frequency difference between a first clock signal in a first synchronous processing apparatus and a second clock signal in the wireless communication apparatus according to a first message exchanged between the first synchronous processing apparatus and the wireless communication apparatus, calculate a correction amount based on a phase difference between a first time in a second synchronous processing apparatus and a second time in the wireless communication apparatus according to a second message exchanged between the second synchronous processing apparatus and the wireless communication apparatus, and when a failure is detected in the first synchronous processing apparatus based on the variation amount and the correction amount, switch an object for synchronization from the first synchronous processing apparatus to the second synchronous processing apparatus.Type: ApplicationFiled: August 7, 2017Publication date: March 1, 2018Applicant: FUJITSU LIMITEDInventors: Kenji KAZEHAYA, Mitsurou NAKAJIMA, Shigeaki KAWAMATA, Yoshinobu IMAI, Jun ROPPONGI
-
Publication number: 20170150464Abstract: A communication apparatus, for relaying a time synchronizing signal between a master and a slave that transmit PTP (Precision Time Protocol) signals, stores a first time of the communication apparatus at a point in time that the communication apparatus receives a first time synchronizing signal addressed to the slave, obtains a second time of the master at a point in time that the first time synchronizing signal is transmitted from the master, from the first time synchronizing signal or the like, obtains an amount of offset that is a difference between a reference time of the master and a reference time of the communication apparatus, using the first time as a time of the slave and the second time as the time of the master in a time synchronizing algorithm of the PTP, and corrects the reference time of the communication apparatus using the amount of offset.Type: ApplicationFiled: October 7, 2016Publication date: May 25, 2017Inventors: Kenji KAZEHAYA, Shigeaki KAWAMATA, Yuichiro KATAGIRI, Masumi KOBAYASHI
-
Patent number: 9654113Abstract: A control device for a clock generation circuit that generates a clock signal based on a reference signal from an outside, the control device includes: a storage device that stores frequency correction information for the clock signal according to a temperature condition of the clock generation circuit; and a processor that controls a frequency of the clock signal generated by the clock generation circuit under a second temperature condition, based on first and second frequency correction information according to a first temperature condition at first and second time points in the storage device.Type: GrantFiled: September 9, 2015Date of Patent: May 16, 2017Assignee: FUJITSU LIMITEDInventors: Masumi Kobayashi, Shigeaki Kawamata, Kenji Kazehaya, Yuichiro Katagiri
-
Publication number: 20170127363Abstract: A radio equipment controller (REC) includes a transmission serializer/deserializer (SERDES), a reception SERDES, and an adjustment unit. The adjustment unit adjusts a transmission timing of a downlink frame to be transmitted from the transmission SERDES in the REC so that the transmission timing of the downlink frame from an antenna of radio equipment (RE) becomes a predetermined timing after synchronization of a downlink and an uplink is established. The RE includes a transmission SERDES, a reception SERDES, and a control unit. The control unit causes the transmission SERDES in the RE to start transmitting an uplink frame after the synchronization of the downlink is established with the REC. The control unit also causes the transmission SERDES in the RE to maintain a transmission timing of the uplink frame, even if a synchronization loss of the downlink is detected due to adjustment of the transmission timing of the downlink frame.Type: ApplicationFiled: September 21, 2016Publication date: May 4, 2017Applicant: FUJITSU LIMITEDInventors: Kazushi Tamamoto, SHIGEAKI KAWAMATA, NOBUYUKI FUKUDA, Toshihiro Kobayashi
-
Publication number: 20170064661Abstract: A base station system includes a radio control device and a radio device, the radio control device transmits first time information and data to the radio device, the radio device includes an antenna and is configured to receive the first time information and the data generate second time information synchronized with the first time information based on the first time information, store the data into a buffer, identify, based on the second time information, a first timing when the data is to be transmitted from the antenna, identify, based on a difference between the first timing and a second timing specified based on a system clock recovered from the received data, a third timing when the data is to be read from the buffer, read the data stored in the buffer at the identified third timing, and control the antenna to transmit the data read from the buffer.Type: ApplicationFiled: August 8, 2016Publication date: March 2, 2017Inventors: Yuichiro KATAGIRI, Shigeaki Kawamata, Kenji Kazehaya, Masumi Kobayashi
-
Patent number: 9411968Abstract: A communication apparatus performs encryption on data transmitted from another communication apparatus by using first or second cryptographic algorithm, or performs decryption on the data that has been encrypted using the first or second cryptographic algorithm, by using one of the first and second cryptographic algorithms used for the encryption, where the second cryptographic algorithm provides a higher security level than the first cryptographic algorithm. The communication apparatus includes an encryption unit configured to perform, upon receiving the data including a cryptographic class identifying a parameter to be used for performing the encryption or the decryption, the encryption or the decryption by using one of the first and second cryptographic algorithms, based on the cryptographic class.Type: GrantFiled: August 30, 2013Date of Patent: August 9, 2016Assignee: FUJITSU LIMITEDInventors: Isamu Fukuda, Shigeaki Kawamata, Jun Roppongi, Akihiro Kameda, Kazuyuki Minohara, Nobuyuki Fukuda
-
Patent number: 9367698Abstract: A communication apparatus performs encryption on data transmitted from another communication apparatus by using first or second cryptographic algorithm, or performs decryption on the data that has been encrypted using the first or second cryptographic algorithm, by using one of the first and second cryptographic algorithms used for the encryption, where the second cryptographic algorithm provides a higher security level than the first cryptographic algorithm. The communication apparatus includes an encryption unit configured to perform, upon receiving the data including a cryptographic class identifying a parameter to be used for performing the encryption or the decryption, the encryption or the decryption by using one of the first and second cryptographic algorithms, based on the cryptographic class.Type: GrantFiled: August 30, 2013Date of Patent: June 14, 2016Assignee: FUJITSU LIMITEDInventors: Isamu Fukuda, Shigeaki Kawamata, Jun Roppongi, Akihiro Kameda, Kazuyuki Minohara, Nobuyuki Fukuda
-
Publication number: 20160099716Abstract: A control device for a clock generation circuit that generates a clock signal based on a reference signal from an outside, the control device includes: a storage device that stores frequency correction information for the clock signal according to a temperature condition of the clock generation circuit; and a processor that controls a frequency of the clock signal generated by the clock generation circuit under a second temperature condition, based on first and second frequency correction information according to a first temperature condition at first and second time points in the storage device.Type: ApplicationFiled: September 9, 2015Publication date: April 7, 2016Inventors: Masumi KOBAYASHI, Shigeaki Kawamata, Kenji Kazehaya, Yuichiro Katagiri
-
Publication number: 20150365340Abstract: A packet transmission apparatus includes: while data included in a preceding packet having a low priority is being transmitted without fragmentation, when time has come to transmit a succeeding packet having a priority higher than that of the preceding packet, one or more processors configured to perform conversion processing for dividing the preceding packet into a plurality of fragment packets while the data is being transmitted; and a transmission unit configured to transmit the succeeding packet between a first fragment packet, and a second fragment packet among the plurality of fragment packets.Type: ApplicationFiled: May 12, 2015Publication date: December 17, 2015Inventors: Nobuyuki FUKUDA, Shigeaki KAWAMATA, Yutaka AOYAMA, Masumi KOBAYASHI
-
Publication number: 20140136853Abstract: A communication apparatus performs encryption on data transmitted from another communication apparatus by using first or second cryptographic algorithm, or performs decryption on the data that has been encrypted using the first or second cryptographic algorithm, by using one of the first and second cryptographic algorithms used for the encryption, where the second cryptographic algorithm provides a higher security level than the first cryptographic algorithm. The communication apparatus includes an encryption unit configured to perform, upon receiving the data including a cryptographic class identifying a parameter to be used for performing the encryption or the decryption, the encryption or the decryption by using one of the first and second cryptographic algorithms, based on the cryptographic class.Type: ApplicationFiled: August 30, 2013Publication date: May 15, 2014Applicant: FUJITSU LIMITEDInventors: Isamu FUKUDA, Shigeaki Kawamata, Jun Roppongi, Akihiro Kameda, Kazuyuki Minohara, Nobuyuki Fukuda
-
Patent number: 8400965Abstract: In a radio base station apparatus that connects a radio control device and plural radio devices to each other through plural links and transmits and receives data by using a frame, a synchronization unit calculates a difference between a first reference counter and a second reference counter from first and second transmission values and first and second reception values and corrects a count value of the second reference counter based on the difference so as to make the count value of the second reference counter coincide with a count value of the first reference counter.Type: GrantFiled: January 26, 2010Date of Patent: March 19, 2013Assignee: Fujitsu LimitedInventors: Yutaka Aoyama, Shigeaki Kawamata
-
Publication number: 20100246487Abstract: In a radio base station apparatus that connects a radio control device and plural radio devices to each other through plural links and transmits and receives data by using a frame, a synchronization unit calculates a difference between a first reference counter and a second reference counter from first and second transmission values and first and second reception values and corrects a count value of the second reference counter based on the difference so as to make the count value of the second reference counter coincide with a count value of the first reference counter.Type: ApplicationFiled: January 26, 2010Publication date: September 30, 2010Applicant: FUJITSU LIMITEDInventors: Yutaka AOYAMA, Shigeaki KAWAMATA
-
Patent number: 6345320Abstract: A system includes a main-memory unit, an input/output-control unit which performs a write operation with respect to the main-memory unit by way of direct memory access, and a central-control unit which operates based on information stored in the main-memory unit, the central-control unit including a cache memory which temporarily stores some of the information, and a DMA buffer which temporarily stores a DMA address indicated by the direct memory access.Type: GrantFiled: October 1, 1998Date of Patent: February 5, 2002Assignee: Fujitsu LimitedInventors: Shigeaki Kawamata, Atsushi Yoshioka