Patents by Inventor Shigeaki Noumi
Shigeaki Noumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7405783Abstract: A display apparatus according to the present invention is provided with a gate line 2 formed on an insulating substrate, a source line 13 intersecting with the gate line 2 with an insulating film in between, a source electrode 6 connected to the source line 13, a drain electrode 10 connected to a pixel electrode 9, a semiconductor layer 4 formed below the source electrode 6, the source line 13, and the drain electrode 10, a light-shielding pattern 12 configured below the semiconductor layer 4 lying below the source line 13, and a backlight emitting lights from a light source to the surface of the insulating substrate opposite to where pixels are formed. In this configuration, leakage current arisen in the semiconductor layer lying below the source line, the extending pattern of the drain electrode, and so on can be suppressed.Type: GrantFiled: June 7, 2005Date of Patent: July 29, 2008Assignee: Mitsubishi Electric CorporationInventors: Hironori Aoki, Shigeaki Noumi, Takafumi Hashiguchi
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Publication number: 20080131668Abstract: An array substrate has regions in which an intermediate resist film thickness is formed and processed by an intermediate exposure amount which does not completely expose a resist, respectively on a drain electrode, source terminal, and a common connection wiring which are made of a second conductive film. Thin film patterns or a common wiring made of a first conductive film is formed in substantially entire regions on the bottom layers of the regions so that the heights from a substrate are substantially the same.Type: ApplicationFiled: November 21, 2007Publication date: June 5, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yuichi MASUTANI, Shigeaki Noumi, Takeshi Shimamura, Masaru Aoki
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Publication number: 20070103625Abstract: A thin film transistor array substrate includes a reflective electrode, a storage capacitor electrode disposed below the reflective electrode with a first insulation layer interposed therebetween, a second insulation layer disposed above the reflective electrode, the second insulation layer having a contact hole in an area where the storage capacitor electrode is not disposed, a transmissive electrode electrically connected to the reflective electrode through the contact hole, and a thickness compensation pattern disposed below the reflective electrode in an area having the contact hole. The thickness compensation pattern is isolated from the storage capacitor electrode.Type: ApplicationFiled: October 11, 2006Publication date: May 10, 2007Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yuichi MASUTANI, Shigeaki NOUMI, Shingo NAGANO
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Patent number: 7206056Abstract: The display device includes the lead line connected to pixels, the line terminal connected to the lead line and connected to the terminal of the drive circuit mounted directly on the insulating substrate by the conductive material through the transparent conductive film, the external terminal to be connected to an external unit, an external line connected to the external terminal, and an external line terminal connected to the external line and connected directly to the terminal of the drive circuit by the conductive material. The surface of the line terminal to be connected to the transparent conductive film is formed by the high resistance conductive film, and the surface of the external line terminal to be connected to the terminal of the drive circuit by the conductive material is formed by the low resistance conductive film.Type: GrantFiled: April 12, 2004Date of Patent: April 17, 2007Assignee: Advanced Display Inc.Inventors: Hitoshi Morishita, Hiroshi Ueda, Hirofumi Iwanaga, Shigeaki Noumi, Takehisa Yamaguchi
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Publication number: 20070040981Abstract: The present invention provides a display device which has a narrow screen border, and excellent display equality. The display device according to the present invention comprises a display panel comprising a glass substrate and a source driver IC which is provided along the edge of the glass substrate. The FPC is connected between the source driver ICs. At the substrate end side of the source driver IC, a bump for GND, a bump for analog power supply, a bump for digital power supply, a bump for reference voltage at the positive polarity side, and a bump for reference voltage at the negative polarity side are formed sequentially from the outer side along the flow of current. These bumps for input and the FPC are connected with the lines for input on the glass substrate. The logic signal lines and are formed along the short side of the source driver IC and along the long side at the display area side.Type: ApplicationFiled: October 25, 2006Publication date: February 22, 2007Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Hirofumi Iwanaga, Shigeaki Noumi, Hitoshi Morishita, Hiroshi Ueda
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Publication number: 20070040980Abstract: The present invention provides a display device which has a narrow screen border, and excellent display equality. The display device according to the present invention comprises a display panel comprising a glass substrate and a source driver IC which is provided along the edge of the glass substrate. The FPC is connected between the source driver ICs. At the substrate end side of the source driver IC, a bump for GND, a bump for analog power supply, a bump for digital power supply, a bump for reference voltage at the positive polarity side, and a bump for reference voltage at the negative polarity side are formed sequentially from the outer side along the flow of current. These bumps for input and the FPC are connected with the lines for input on the glass substrate. The logic signal lines and are formed along the short side of the source driver IC and along the long side at the display area side.Type: ApplicationFiled: October 25, 2006Publication date: February 22, 2007Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Hirofumi Iwanaga, Shigeaki Noumi, Hitoshi Morishita, Hiroshi Ueda
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Publication number: 20070013856Abstract: The present invention provides a flexible printed circuit that is less likely to suffer from erosion (corrosion) of electrode terminals even in severe environments and a display device using the flexible printed circuit. According to the present invention, a flexible printed circuit includes a flexible FPC film, FPC interconnections formed of a given pattern on the FPC film, a solder resist covering the FPC interconnections, and FPC terminals provided at ends of the FPC interconnections to make external connection. According to the invention, the FPC terminals include at least one terminal that has an end located inside of an outline of the FPC film.Type: ApplicationFiled: May 16, 2006Publication date: January 18, 2007Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Kenichi Watanabe, Hiroshi Ueda, Hiroshi Tachibana, Shigeaki Noumi
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Publication number: 20070001944Abstract: An object of the present invention is to provide an image display device that is free from disconnection in a connection structure between given substrates even when operated in a hot and humid environment. An image display device according to a preferred embodiment of the invention has a TFT substrate and an FPC. The TFT substrate has a plurality of first terminals capable of application of potential. The FPC has second terminals that are connected respectively with the first terminals through an anisotropic conductive film and that are thicker than the first terminals. The second terminals include a high-potential terminal, a low-potential terminal, and a dummy terminal. The high-potential terminal is supplied with a relatively high potential that contributes to the display operation. The low-potential terminal is supplied with a relatively low potential that contributes to the display operation.Type: ApplicationFiled: February 21, 2006Publication date: January 4, 2007Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hiroshi Ueda, Hitoshi Morishita, Shigeaki Noumi
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Publication number: 20060233003Abstract: A matrix display device includes an array substrate which controls switching elements connected to pixel electrodes surrounded by gate and source lines by a select signal, and supplies a video signal to the pixel electrodes, a unit that switches between a first and a second scan modes according to an input signal, flexible substrates provided with a gate driver for supplying a signal to the gate line and electrode terminals, and gate control signal lines formed on the array substrate and connecting together corresponding electrode terminals on adjacent flexible substrates. The electrode terminals are formed along single edges of the flexible substrates on a side of the array substrate. The gate control signal lines are formed on an opposite side of the gate driver. The gate control signal line includes first and second gate scan start signal lines which become active during first and second scan modes, respectively.Type: ApplicationFiled: February 24, 2006Publication date: October 19, 2006Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hirofumi Iwanaga, Shigeaki Noumi, Hiroshi Ueda
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Publication number: 20060215067Abstract: Yield in mounting a FPC onto an insulating substrate is increased as well as noise is suppressed, thereby the display device having high quality can be obtained. The display device includes: an insulating substrate on which a display region having pixels is formed; signal wires formed on the insulating substrate and connected to the pixels in the display region; terminals formed, in order to supply signals to the signal wires, outside the display region on the insulating substrate; a driving circuit 3 directly connected to the terminals or a driving circuit connected to the terminals via a film; and a resistor element 9 formed, on the insulating substrate, between adjacent input signal wires 5 for inputting signals to the driving circuit 3.Type: ApplicationFiled: February 22, 2006Publication date: September 28, 2006Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hiroshi Ueda, Hirofumi Iwanaga, Shigeaki Noumi, Hitoshi Morishita
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Publication number: 20050286005Abstract: A liquid crystal display of the present invention comprises a display portion having two opposed insulating substrates (an electrode substrate (1) and an opposed substrate 2) holding a liquid crystal layer to form a plurality of display elements, wires (3a) formed on at least one of the insulating substrates, for supplying signals to the plurality of display elements, a driver LSI (6) provided in a peripheral portion of the insulating substrate, being connected to terminals of the wires (3a, 3b) to drive a plurality of display elements, and a conductive film pattern portion formed on the wires (3a) in the peripheral portion of the insulating substrate with a first insulating layer interposed therebetween. With this constitution, a liquid crystal display which allows inspection of output signals of the driver LSI in a failure analysis, without extending wires or exposing electrode portions connected to the wires and a method of inspecting the liquid crystal display are provided.Type: ApplicationFiled: June 14, 2005Publication date: December 29, 2005Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Kenichi Watanabe, Yuichi Masutani, Shigeaki Noumi, Hitoshi Morishita, Hiroshi Ueda
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Publication number: 20050230719Abstract: A display apparatus according to the present invention is provided with a gate line 2 formed on an insulating substrate, a source line 13 intersecting with the gate line 2 with an insulating film in between, a source electrode 6 connected to the source line 13, a drain electrode 10 connected to a pixel electrode 9, a semiconductor layer 4 formed below the source electrode 6, the source line 13, and the drain electrode 10, a light-shielding pattern 12 configured below the semiconductor layer 4 lying below the source line 13, and a backlight emitting lights from a light source to the surface of the insulating substrate opposite to where pixels are formed. In this configuration, leakage current arisen in the semiconductor layer lying below the source line, the extending pattern of the drain electrode, and so on can be suppressed.Type: ApplicationFiled: June 7, 2005Publication date: October 20, 2005Applicant: ADVANCED DISPLAY INC.Inventors: Hironori Aoki, Shigeaki Noumi, Takafumi Hashiguchi
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Patent number: 6919942Abstract: A display apparatus according to the present invention is provided with a gate line 2 formed on an insulating substrate, a source line 13 intersecting with the gate line 2 with an insulating film in between, a source electrode 6 connected to the source line 13, a drain electrode 10 connected to a pixel electrode 9, a semiconductor layer 4 formed below the source electrode 6, the source line 13, and the drain electrode 10, a light-shielding pattern 12 configured below the semiconductor layer 4 lying below the source line 13, and a backlight emitting lights from a light source to the surface of the insulating substrate opposite to where pixels are formed. In this configuration, leakage current arisen in the semiconductor layer lying below the source line, the extending pattern of the drain electrode, and so on can be suppressed.Type: GrantFiled: September 9, 2002Date of Patent: July 19, 2005Assignee: Advanced Display Inc.Inventors: Hironori Aoki, Shigeaki Noumi, Takafumi Hashiguchi
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Publication number: 20040246427Abstract: The present invention provides a display device which has a narrow screen border, and excellent display equality. The display device according to the present invention comprises a display panel comprising a glass substrate and a source driver IC which is provided along the edge of the glass substrate. The FPC is connected between the source driver ICs. At the substrate end side of the source driver IC, a bump for GND, a bump for analog power supply, a bump for digital power supply, a bump for reference voltage at the positive polarity side, and a bump for reference voltage at the negative polarity side are formed sequentially from the outer side along the flow of current. These bumps for input and the FPC are connected with the lines for input on the glass substrate. The logic signal lines and are formed along the short side of the source driver IC and along the long side at the display area side.Type: ApplicationFiled: June 3, 2004Publication date: December 9, 2004Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Hirofumi Iwanaga, Shigeaki Noumi, Hitoshi Morishita, Hiroshi Ueda
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Publication number: 20040207796Abstract: The display device includes the lead line connected to pixels, the line terminal connected to the lead line and connected to the terminal of the drive circuit mounted directly on the insulating substrate by the conductive material through the transparent conductive film, the external terminal to be connected to an external unit, an external line connected to the external terminal, and an external line terminal connected to the external line and connected directly to the terminal of the drive circuit by the conductive material. The surface of the line terminal to be connected to the transparent conductive film is formed by the high resistance conductive film, and the surface of the external line terminal to be connected to the terminal of the drive circuit by the conductive material is formed by the low resistance conductive film.Type: ApplicationFiled: April 12, 2004Publication date: October 21, 2004Applicant: ADVANCED DISPLAY INC.Inventors: Hitoshi Morishita, Hiroshi Ueda, Hirofumi Iwanaga, Shigeaki Noumi, Takehisa Yamaguchi
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Publication number: 20030178628Abstract: A display apparatus according to the present invention is provided with a gate line 2 formed on an insulating substrate, a source line 13 intersecting with the gate line 2 with an insulating film in between, a source electrode 6 connected to the source line 13, a drain electrode 10 connected to a pixel electrode 9, a semiconductor layer 4 formed below the source electrode 6, the source line 13, and the drain electrode 10, a light-shielding pattern 12 configured below the semiconductor layer 4 lying below the source line 13, and a backlight emitting lights from a light source to the surface of the insulating substrate opposite to where pixels are formed. In this configuration, leakage current arisen in the semiconductor layer lying below the source line, the extending pattern of the drain electrode, and so on can be suppressed.Type: ApplicationFiled: September 9, 2002Publication date: September 25, 2003Applicant: ADVANCED DISPLAY INC.Inventors: Hironori Aoki, Shigeaki Noumi, Takafumi Hashiguchi
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Patent number: 6353464Abstract: A manufacturing method of a liquid crystal display is provided. The liquid crystal display having a picture element electrode formed on the uppermost layer of a structure is capable of reducing connection resistance between picture element electrode and drain electrode through interlayer insulating film. At the time of forming the picture element electrode, ITO film can be patterned into a desirable pattern without short circuit between assembled terminals in one etching process. In the process of forming a contact hole 112 for connecting the picture element electrode 113 and the drain electrode 108 on the interlayer insulating film 111 and on the passivation film 110, a dry etching condition is established so that after the ashing process using O2 gas to remove residue on the bottom of the contact hole 112, an etching process using fluorine gas +O2 gas etc. is performed to reduce irregularity on the surface of the interlayer insulating film 111.Type: GrantFiled: November 9, 1999Date of Patent: March 5, 2002Assignee: Kabushiki Kaisha Advanced DisplayInventors: Shigeaki Noumi, Kouji Yabushita
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Patent number: 6317174Abstract: A manufacturing method of a liquid crystal display is provided. The liquid crystal display having a picture element electrode formed on the uppermost layer of a structure is capable of reducing connection resistance between picture element electrode and drain electrode through interlayer insulating film. At the time of forming the picture element electrode, ITO film can be patterned into a desirable pattern without short circuit between assembled terminals in one etching process. In the process of forming a contact hole 112 for connecting the picture element electrode 113 and the drain electrode 108 on the interlayer insulating film 111 and on the passivation film 110, a dry etching condition is established so that after the ashing process using O2 gas to remove residue on the bottom of the contact hole 112, an etching process using fluorine gas+O2 gas etc. is performed to reduce irregularity on the surface of the interlayer insulating film 111.Type: GrantFiled: September 22, 2000Date of Patent: November 13, 2001Assignee: Kabushiki Kaisha Advanced DisplayInventors: Shigeaki Noumi, Kouji Yabushita
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Patent number: 6218206Abstract: To provide a method of producing a TFT array and a liquid crystal display apparatus in which a contact resistivity of a pixel electrode and a drain electrode through a contact hole in an interlayer insulating film can be not more than 10E4&OHgr; stably.Type: GrantFiled: September 15, 1998Date of Patent: April 17, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazunori Inoue, Masaru Aoki, Munehito Kumagai, Shigeaki Noumi, Tohru Takeguchi
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Patent number: 5915172Abstract: Method for manufacturing TFTs including steps of forming a control electrode and control electrode line on a substrate, forming insulating film on the control electrode and the control electrode line, cleaning the substrate with the insulating film formed by a chemical or physical means, forming oxide film on the surface of the control electrode and control electrode line exposed by a film lacking portion generated in the insulating film after cleaning, forming a semiconductor layer via the insulating film on the control electrode, and forming a pair of electrodes constituting a semiconductor element together with the semiconductor layer.Type: GrantFiled: July 8, 1997Date of Patent: June 22, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigeaki Noumi, Kazuhiko Noguchi, Takeshi Kubota, Masami Hayashi, Takeshi Morita