Patents by Inventor Shigeaki Shimizu

Shigeaki Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818813
    Abstract: In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR. An n-type semiconductor layer NR1 is formed over the semiconductor layer EP. The semiconductor layer PR, the semiconductor layer EP, and the semiconductor layer NR1 respectively configure part of a photoreceiver. A cap layer of a material different from that of the semiconductor layer EP is formed over the semiconductor layer EP, and a silicide layer, which is a reaction product of a metal and the material included in the cap layer, is formed within the cap layer. A plug having a barrier metal film BM1 is formed over the cap layer through the silicide layer. Here, a reaction product of the metal and the material included in the semiconductor layer NR1 is not formed within the semiconductor layer NR1.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: October 27, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoo Nakayama, Shinichi Watanuki, Futoshi Komatsu, Teruhiro Kuwajima, Takashi Ogura, Hiroyuki Okuaki, Shigeaki Shimizu
  • Publication number: 20190198703
    Abstract: In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR. An n-type semiconductor layer NR1 is formed over the semiconductor layer EP. The semiconductor layer PR, the semiconductor layer EP, and the semiconductor layer NR1 respectively configure part of a photoreceiver. A cap layer of a material different from that of the semiconductor layer EP is formed over the semiconductor layer EP, and a silicide layer, which is a reaction product of a metal and the material included in the cap layer, is formed within the cap layer. A plug having a barrier metal film BM1 is formed over the cap layer through the silicide layer. Here, a reaction product of the metal and the material included in the semiconductor layer NR1 is not formed within the semiconductor layer NR1.
    Type: Application
    Filed: November 13, 2018
    Publication date: June 27, 2019
    Inventors: Tomoo NAKAYAMA, Shinichi WATANUKI, Futoshi KOMATSU, Teruhiro KUWAJIMA, Takashi OGURA, Hiroyuki OKUAKI, Shigeaki SHIMIZU
  • Patent number: 9589954
    Abstract: Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first recess therein. The first recess is located between the gate insulating film and the drain region, and is filled with an insulating film. The insulating film has a second recess on its side close to the gate insulating film. An angle defined by an inner side face of the first recess and the surface of the substrate is rounded on a side of the drain region close to the gate insulating film.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: March 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Mitsuiki, Tomoo Nakayama, Shigeaki Shimizu, Hiroyuki Okuaki
  • Publication number: 20160056233
    Abstract: Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first recess therein. The first recess is located between the gate insulating film and the drain region, and is filled with an insulating film. The insulating film has a second recess on its side close to the gate insulating film. An angle defined by an inner side face of the first recess and the surface of the substrate is rounded on a side of the drain region close to the gate insulating film.
    Type: Application
    Filed: August 5, 2015
    Publication date: February 25, 2016
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Akira MITSUIKI, Tomoo NAKAYAMA, Shigeaki SHIMIZU, Hiroyuki OKUAKI
  • Patent number: 8455925
    Abstract: To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M>N), capacitance elements are provided over the interconnect layers comprised of (M?N) layers or (M?N+1) layers.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: June 4, 2013
    Assignee: Renesas Electronic Coporation
    Inventors: Masashige Moritoki, Takamasa Itou, Takashi Ogura, Tsutomu Himukai, Shigeaki Shimizu
  • Publication number: 20110193136
    Abstract: To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M>N), capacitance elements are provided over the interconnect layers comprised of (M?N) layers or (M?N+1) layers.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 11, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Masashige MORITOKI, Takamasa ITOU, Takashi OGURA, Tsutomu HIMUKAI, Shigeaki SHIMIZU
  • Patent number: 5227642
    Abstract: A symbol/character discrimination apparatus having a dark-field light source for applying light beams at a predetermined angle of incidence to the surface of a sample on which symbols and/or characters are formed in an indentation pattern, a CCD camera for detecting reflected light beams from the sample surface, and a condensing lens for illumination, diaphragm, and objective optical lens for detection, arranged between the CCD camera and the sample and having a common optical axis. The condensing lens is located between the light source and the sample to condense the light beams from the light source on the surface of the sample and guides the reflected light beams from the sample to the diaphragm. The diaphragm intercepts regularly reflected light beams among the reflected light beams and guides some of the irregularly reflected light beams to the objective optical lens for detection. The objective optical lens guides some of the irregularly reflected light beams to the CCD camera.
    Type: Grant
    Filed: December 31, 1991
    Date of Patent: July 13, 1993
    Assignee: Tokyo Electron Yamanashi Limited
    Inventor: Shigeaki Shimizu
  • Patent number: 4604260
    Abstract: A solid electrolytic capacitor is made with an Aluminum-titanium body. Aluminum and titanium powders are press-molded into a body which is then heated sufficiently to provide a porous Al-Ti alloy with an oxide layer. Next, the body is heated in an atmosphere containing at least 0.1% by volume of oxygen at a temperature in the range of about 500.degree.-700.degree. C. Thereafter, a layer of manganese dioxide is formed over the oxide layer and a cathode electrode layer is then formed over the manganese dioxide layer.
    Type: Grant
    Filed: May 22, 1985
    Date of Patent: August 5, 1986
    Assignee: NEC Corporation
    Inventors: Shigeaki Shimizu, Yoshio Arai
  • Patent number: 4517727
    Abstract: A porous sintered body for an aluminum-titanium alloy electrolytic capacitor has a wire of nitrogenized titanium, or the like, implanted therein. A method of producing such a porous body subjects a titanium wire to a nitriding treatment, and embeds the nitrogenized Ti wire into a press-molded body of the mixture of aluminum and either titanium or titanium hydride powders. Then, the press-molded body is sintered. An excellent LC characteristic is obtained even under the sintering condition, and the aluminum-titanium electrolytic capacitor is devoid of bent lead wires.
    Type: Grant
    Filed: June 28, 1983
    Date of Patent: May 21, 1985
    Assignee: NEC Corporation
    Inventors: Shigeaki Shimizu, Yoshimi Kubo, Yoshio Arai, Tetsuo Suzuki, Hitoshi Igarashi
  • Patent number: 4468719
    Abstract: A porous body of Ti-Al alloy has a novel structure for a solid electrolytic capacitor, having improved values of leakage current and dielectric loss. The porous body of Ti-Al alloy has spherical particles which partially contact each other to form an integral body. The surfaces of the spherical particles have a ruggedness in the order of several microns or less. Because the diameter of the spherical particle is greater than the size of the ruggedness, the porous body has rough voids which provide a wide passageway through which a manganese nitrate solution penetrates. The wide passageway is effective for decreasing the number of times when there is a thermal decomposition of the manganese nitrate, thereby reducing the series resistance of the resultant cathode. In addition, this novel structure makes it possible to avoid production difficulties which are usually encountered when a solid electrolytic capacitor, having a high capacitance, is produced from a finely divided Ti-Al alloy.
    Type: Grant
    Filed: April 2, 1981
    Date of Patent: August 28, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Shigeaki Shimizu, Yoshimi Kubo, Tetsuo Suzuki, Takashi Kizaki, Hitoshi Igarashi
  • Patent number: 4432935
    Abstract: A porous body, for a solid electrolytic capacitor, is made from a combination of titanium and aluminum in order to reduce dependence upon tatalum, a material which is now in extremely short supply. First, the titanium hydride and aluminum are milled into an extremely fine micro-powder. Then, the powders are mixed with the aluminum content in the range of 45%-65%, compressed into the desired body shape, and given a three-step heat treatment. In the first step, the body is heated at a temperature of 400.degree. to 500.degree. C. for a dehydrogenation. In the second step, the dehydrogenated body is heated to an alloying temperature which is higher than 500.degree. C., but lower than the melting point of aluminum. In the third step, the alloyed body is heated to a temperature which is higher than the melting point of aluminum (about 1000.degree. C.).
    Type: Grant
    Filed: March 31, 1981
    Date of Patent: February 21, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Yoshimi Kubo, Shigeaki Shimizu, Tetsuo Suzuki, Hitoshi Igarashi